C28 General-Purpose Input/Output (GPIO)
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SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
accidentally change the level of another pin. For example, if you mean to change the output latch level
of GPIOA1 by writing to the GPADAT register bit 0 using a read-modify-write instruction, a problem can
occur if another I/O port A signal changes level between the read and the write stage of the instruction.
Following is an analysis of why this happens:
The GPxDAT registers reflect the state of the pin, not the latch. This means the register reflects the
actual pin value. However, there is a lag between when the register is written to when the new pin
value is reflected back in the register. This may pose a problem when this register is used in
subsequent program statements to alter the state of GPIO pins. An example is shown below where two
program statements attempt to drive two different GPIO pins that are currently low to a high state.
If Read-Modify-Write operations are used on the GPxDAT registers, because of the delay between the
output and the input of the first instruction (I1), the second instruction (I2) will read the old value and
write it back.
GpioDataRegs.GPADAT.bit.GPIO1 = 1 ;
I1 performs read-modify-write of GPADAT GpioDataRegs.GPADAT.bit.GPIO2 = 1 ;
I2 also a read-modify-write of GPADAT. ;
It gets the old value of GPIO1 due to the delay
The second instruction will wait for the first to finish its write due to the write-followed-by-read
protection on this peripheral frame. There will be some lag, however, between the write of (I1) and the
GPxDAT bit reflecting the new value (1) on the pin. During this lag, the second instruction will read the
old value of GPIO1 (0) and write it back along with the new value of GPIO2 (1). Therefore, GPIO1 pin
stays low.
One solution is to put some NOP’s between instructions. A better solution is to use the
GPxSET/GPxCLEAR/GPxTOGGLE registers instead of the GPxDAT registers. These registers always
read back a 0 and writes of 0 have no effect. Only bits that need to be changed can be specified
without disturbing any other bit(s) that are currently in the process of changing.
•
GPxSET/AIOSET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O
port has one set register and each bit corresponds to one GPIO pin. The set registers always read
back 0. If the corresponding pin is configured as an output, then writing a 1 to that bit in the set register
will set the output latch high and the corresponding pin will be driven high. If the pin is not configured
as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later
configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in
the set registers has no effect.
•
GPxCLEAR/AIOCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O
port has one clear register. The clear registers always read back 0. If the corresponding pin is
configured as a general purpose output, then writing a 1 to the corresponding bit in the clear register
will clear the output latch and the pin will be driven low. If the pin is not configured as a GPIO output,
then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO
output will the latched value will be driven onto the pin. Writing a 0 to any bit in the clear registers has
no effect.
•
GPxTOGGLE/AIOTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other
pins. Each I/O port has one toggle register. The toggle registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the toggle register flips the
output latch and pulls the corresponding pin in the opposite direction. That is, if the output pin is driven
low, then writing a 1 to the corresponding bit in the toggle register will pull the pin high. Likewise, if the
output pin is high, then writing a 1 to the corresponding bit in the toggle register will pull the pin low. If
the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven.
Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin.
Writing a 0 to any bit in the toggle registers has no effect.
