Functional Description
1152
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Micro Direct Memory Access ( µDMA)
Table 16-1. µDMA Channel Assignment Mapping (continued)
DMACHALT Encoding
0
1
DMACHMAPx Encoding
0
1
2
µDMA Channel
First Assignment
Second Assignment
Third Assignment
26
Available for software
Reserved
Reserved
27
Available for software
Reserved
Reserved
28
Reserved
Available for software
Reserved
29
Reserved
Available for software
Reserved
30
Dedicated for software use
Reserved
31
Reserved
Reserved
NOTE:
There is another register, DMACHALT, which controls the channel assignments for the First
and Second mapping Only (not Third Mapping). This is for compatibility with Stellaris
devices. The register (DMACHALT vs DMACHMAPx) which is written later, controls the
channel assignment mapping.
16.3.2 Priority
The µDMA controller assigns priority to each channel based on the channel number and the priority level
bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the
priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority:
default priority and high priority. If the priority level bit is set, then that channel has higher priority than all
other channels at default priority. If multiple channels are set for high priority, then the channel number is
used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET) register and
cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
16.3.3 Arbitration Size
When a µDMA channel requests a transfer, the µDMA controller arbitrates among all the channels making
a request and services the µDMA channel with the highest priority. Once a transfer begins, it continues for
a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration
size can be configured for each channel, ranging from 1 to 1024 item transfers. After the µDMA controller
transfers the number of items specified by the arbitration size, it then checks among all the channels
making a request and services the channel with the highest priority.
If a lower priority µDMA channel uses a large arbitration size, the latency for higher priority channels is
increased because the µDMA controller completes the lower priority burst before checking for higher
priority requests. Therefore, lower priority channels should not use a large arbitration size for best
response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that are
transferred at any one time in a burst. Here, the term arbitration refers to determination of µDMA channel
priority, not arbitration for the bus. When the µDMA controller arbitrates for the bus, the processor always
takes priority. Furthermore, the µDMA controller is held off whenever the processor must perform a bus
transaction on the same bus, even in the middle of a burst transfer.
16.3.4 Request Types
The µDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral
may support either or both types of requests. A single request means that the peripheral is ready to
transfer one item, while a burst request means that the peripheral is ready to transfer multiple items.
The µDMA controller responds differently depending on whether the peripheral is making a single request
or a burst request. If both are asserted, and the µDMA channel has been set up for a burst transfer, then
the burst request takes precedence.
shows how each peripheral supports the two request
types.
