Data
ALE
(
)
EPI0S30
(
)
EPI0S30
WR
(
)
EPI0S29
RD/ OE
(
)
EPI0S28
Address
(high order, non-muxed)
Muxed
Address/Data
Address
BSEL0/ BSEL1
a
a
BSEL0 and BSEL1 are available in Host-Bus16 mode only.
CS
Data
ALE
(
)
EPI0S30
CS
(
EPI0S30)
WR
(
)
EPI0S29
RD/OE
(
)
EPI0S28
Address
Data
BSEL0/
BSEL1
a
a
BSEL0 and BSEL1 are available in Host-Bus16 mode only.
Host Bus Mode
1213
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
Figure 17-9. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0, ALEHIGH = 1
shows a write cycle with the address and data signals multiplexed (MODE field is 0x0 in the
EPIHBnCFG register). A read cycle would look similar, with the RD strobe being asserted along with CS
and data being latched on the rising edge of RD.
Figure 17-10. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0,
RDHIGH = 0, ALEHIGH = 1
When using ALE with dual CS configuration (CSCFGEXT bit is 0 and the CSCFG field is 0x3 in the
EPIHBnCFG2 register) or quad chip select (CSCFGEXT bit is 1 and CSCSFG is 0x2), the appropriate CS
signal is asserted at the same time as ALE, as shown in
.
