Register Descriptions
1247
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
17.11.10 EPI General-Purpose Configuration 2 (EPIGPCFG2) Register, offset 0x014
NOTE:
The MODE field in the EPICFG register determines which configuration register is accessed
for offsets 0x010 and 0x014.
To access EPIGPCFG2, the MODE field must be 0x0.
This register is used to configure operation while in General-Purpose mode. Note that this register is reset
when the MODE field in the EPICFG register is changed. If another mode is selected and the General-
Purpose mode is selected again, the values must be reinitialized.
Figure 17-37. EPI General-Purpose Configuration 2 (EPIGPCFG2)Register [offset 0x014]
31
30
0
WORD
Reserved
R/W-0
R-0
LEGENR/W-0D: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 17-23. EPI General-Purpose Configuration 2 (EPIGPCFG2) Register Field Descriptions
Bit
Field
Value
Description
31
WORD
Word Access Mode
By default, the EPI controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is
0x0; data bits [15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and
data bits [31:0] when the DSIZE field is 0x3.
When using Word Access mode, the EPI controller can automatically route bytes of data onto the
correct byte lanes such that data can be stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for
DSIZE=0x1. For DSIZE=0x2 or 0x3, this bit must be clear.
0
Word Access mode is disabled.
1
Word Access mode is enabled.
30-0
Reserved
Reserved