Register Descriptions
1239
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
Table 17-20. EPI General-Purpose Configuration (EPIGPCFG) Register Field Descriptions (continued)
Bit
Field
Value
Description
28
RDYEN
Ready Enable
The ready enable signal may only be used with a free-running EPI clock(CLKGATE=0).The external
iRDY signal is sampled on the falling edge of the EPI clock. Setup and hold times must be met to
ensure registration on the next falling EPI clock edge.
This bit is ignored if CLKPIN is 0 or CLKGATE is 1.
0
The external peripheral does not drive an iRDY signal and is assumed to be ready always.
1
The external peripheral drives an iRDY signal into pin EPI0S27.
27
Reserved
Reserved
26
FRM50
50/50 Frame
0
The FRAME signal is output as a single pulse, and then held low for the count.
1
The FRAME signal is output as 50/50 duty cycle using count (see FRMCNT).
25-22
FRMCNT
Frame Count
This field specifies the size of the frame in EPI clocks. The frame counter is used to determine the
frame size. The count is 1.So, a FRMCNT of 0 forms a pure transaction valid signal
(held high during transactions, low otherwise).
A FRMCNT of 0 with FRM50 set inverts the FRAME signal on each transaction. A FRMCNT of 1
means the FRAME signal is inverted every other transaction; a value of 15 means every sixteenth
transaction.
If FRM50 is set, the frame is held high for 1 transactions, then held low for that many
transactions, and so on.
If FRM50 is clear, the frame is pulsed high for one EPI clock and then low for FRMCNT EPI clocks.
This field is ignored if FRMPIN is 0.
21-20
Reserved
Reserved
19
WR2CYC
2-Cycle Writes
When this bit is set, then the RW bit is forced to be set.
0
Data is output on the same EPI clock cycle as the address.
1
Writes are two EPI clock cycles long, with address on one EPI clock cycle (with the WR strobe
asserted) and data written on the following EPI clock cycle (with WR strobe de-asserted). The next
address (if any) is in the cycle following.
18
RD2CYC
2-Cycle Reads
When this bit is set, then the RW bit is forced to be set.
Caution: This bit must be set at all times in General-Purpose mode to ensure proper
operation.
0
Data is captured on the EPI clock cycle with READ strobe asserted.
1
Reads are two EPI clock cycles, with address on one EPI clock cycle (with the RD strobe asserted)
and data captured on the following EPI clock cycle (with the RD strobe de-asserted). The next
address (if any) is in the cycle following.
17-16
Reserved
Reserved
15-8
MAXWAIT
Maximum Wait
This field defines the maximum number of EPI clocks to wait while the iRDY signal (see RDYEN) is
holding off a transaction. If this field is 0, the transaction is held forever. If the maximum wait of 255
clocks (MAXWAIT=0xFF) is exceeded, an error interrupt occurs and the transaction is
aborted/ignored.
Note:
When the MODE field is configured to be 0x0 and the BLKEN bit is set in the EPICFG
register, enabling General-Purpose mode, this field defaults to 0xFF.
7-6
Reserved
Reserved
5-4
ASIZE
Address Bus Size
This field defines the size of the address bus. The address can be up to 4-bits wide with a 24-bit
data bus, up to 12-bits wide with a 16-bit data bus, and up to 20-bits wide with an 8-bit data bus. If
the full address bus is not used, use the least significant address bits. Any unused address bits can
be used as GPIOs by clearing the AFSEL bit for the corresponding GPIOs. Also, if RDYEN is 1,
then the address sizes are 1 smaller (3, 11, 19).
The values are:
0x0
No address.
0x1
Up to 4 bits wide.
0x2
Up to 12 bits wide. This size cannot be used with 24-bit data.
0x3
Up to 20 bits wide. This size cannot be used with data sizes other than 8.
3-2
Reserved
Reserved
