Texas Instruments Concerto F28M35 Series, Technical Reference Manual

Page: 618 / 1655

Guidelines for Boot ROM Application Writers
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618 SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
ROM Code and Peripheral Booting
IPCLiteMtoCSetBits_Protected(IPC_FLAG1, CCORE_L0L4_RAM_INIT_REG_ADDR,
(CCORE_L0_RAM_INIT_BIT| CCORE_L1_RAM_INIT_BIT| CCORE_L2_RAM_INIT_BIT| CCORE_L3_RAM_INIT_BIT),
IPC_LENGTH_32_BITS, IPC_FLAG32);
//wait until C-BootROM acks
while(HWREG(MTOCIP IPC_O_MTOCIPCFLG) and IPC_FLAG1);
//CHECK IF pass or fail
if(HWREG(MTOCIP IPC_O_MTOCIPCFLG) and IPC_FLAG32)
{//still set - so command failed.
//error - blink SLOOOOOOOOWWW
while(1)
{
for(ii = 0; ii < 0xDEADC0DE; ii++);
//ERROR – HAVE an ERROR INDICATOR here
}
}
//WAIT for RAM_INIT done of above memories
do
{
IPCLiteMtoCDataRead(IPC_FLAG1, CCORE_L0_L4_RAM_INIT_DONE_REG_ADDR,
IPC_LENGTH_32_BITS, IPC_FLAG32);
//wait until C-BootROM acks
while(HWREG(MTOCIP IPC_O_MTOCIPCFLG) and IPC_FLAG1);
//CHECK IF pass or fail
if(HWREG(MTOCIP IPC_O_MTOCIPCFLG) and IPC_FLAG32)
{//still set - so command failed.
while(1)
{
for(ii = 0; ii < 0xDEADC0DE; ii++);
//ERROR – HAVE an ERROR INDICATOR here
}
}
else
{
if(HWREG(MTOCIP IPC_O_MTOCIPCDATAR) and
(CCORE_L0_RAM_INIT_DONE_BIT| CCORE_L1_RAM_INIT_DONE_BIT| CCORE_L2_RAM_INIT_DONE_BIT|
CCORE_L3_RAM_INIT_DONE_BIT ))
{
//RAM_INIT completed - do nothing :-)
break;
}
else
{
//RAM_INIT not done yet, so wait for
more time and read ram init done register.
//GIVE some cycles delay until CCORE
performs RAM INIT
for(ii =0 ; ii < 2048; ii++);
continue;
}
}
}while(1);
}