Renesas H8S Family, Hardware Manual

Page: 147 / 1230

Section 5 Interrupt Controller
Rev. 1.00 Mar. 12, 2008 Page 99 of 1178
REJ09B0403-0100
5.6.4 Interrupt Response Times
Table 5.7 shows interrupt response times
−
the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.7 are explained in table 5.8.
Table 5.7 Interrupt Response Times
No. Execution Status Advanced Mode
1 Interrupt priority determination *
1
3
2 Number of wait states until executing instruction ends *
2
1 to (19 + 2·S
I
)
3 PC, CCR stack save 2·S
K
4 Vector fetch 2·S
I
5 Instruction fetch *
3
2·S
I
6 Internal processing *
4
2
Total (using on-chip memory) 12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.8 Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device
8-Bit Bus 16-Bit Bus
Symbol
Internal
Memory
2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch S
I
1 4 6 + 2m 2 3 + m
Branch address read S
J
Stack manipulation S
K
[Legend]
m: Number of wait states in external device access.