Renesas H8S Family, Hardware Manual

Page: 1109 / 1230

Section 28 Power-Down Modes
Rev. 1.00 Mar. 12, 2008 Page 1061 of 1178
REJ09B0403-0100
28.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7, 6

0 R/W Reserved
The initial value should not be changed.
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (
φ
SUB) input
from the EXCL pin is sampled using the clock (
φ
)
generated by the system clock pulse generator.
0: Sampling using
φ
/32 clock
1: Sampling using
φ
/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3

0 R/W Reserved
The initial value should not be changed.
2 PNCCS 0 R/W Address Multiplex Chip Select
Controls the output polarity of chip select signals (
CS256
,
IOS
) in the address multiplex extended mode.
0: Outputs
CS256
, and
IOS
1: Outputs CS256, and IOS
1 PNCAH 0 R/W Address Multiplex Address Hold
Controls the output polarity of the address hold signal (
AH
)
in the address multiplex extended mode.
0: Outputs
AH
1: Outputs AH
0

0 R/W Reserved
The initial value should not be changed.