Renesas H8S Family, Hardware Manual

Page: 205 / 1230

Section 6 Bus Controller (BSC)
Rev. 1.00 Mar. 12, 2008 Page 157 of 1178
REJ09B0403-0100
(2) DTC
The DTC sends the bus arbiter a request for the bus mastership when a request for DTC activation
occurs. The DTC releases the bus mastership after a series of processes has completed.
The DTC is the lower-priority bus master than the E-DMAC, and if a bus mastership request is
received from the E-DMAC, the bus arbiter transfers the bus mastership to the E-DMAC. The
timing for transferring the bus mastership is as follows:
•
Timing for transferring the bus mastership to the E-DMAC
1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
in discrete operations, as in the case of a longword size access, the bus is not transferred at a
break between the operations. In addition, in the case of a 32-bit access by the DTC, the bus is
not transferred at a break between the operations. For details, see section 21, Ethernet
Controller Direct Memory Access Controller (E-DMAC).
2. If the CPU is in sleep mode, it transfers the bus mastership immediately.
(3) E-DMAC
The E-DMAC is the highest-priority bus master, and sends the bus arbiter a request for the bus
when an activation request is generated. The E-DMAC does not release the bus until the
consecutive transfer cycles have completed. For details, see section 21, Ethernet Controller Direct
Memory Access Controller (E-DMAC).