Renesas H8S Family, Hardware Manual

Page: 209 / 1230

Section 7 Data Transfer Controller (DTC)
Rev. 1.00 Mar. 12, 2008 Page 161 of 1178
REJ09B0403-0100
7.2 Register Descriptions
The DTC has the following registers.
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DTC mode register A (MRA)
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DTC mode register B (MRB)
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DTC source address register (SAR)
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DTC destination address register (DAR)
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DTC transfer count register A (CRA)
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DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
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DTC enable registers (DTCER)
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DTC vector register (DTVECR)
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Keyboard comparator control register (KBCOMP)
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Event counter control register (ECCR)
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Event counter status register (ECS)