Renesas H8S Family, Hardware Manual

Page: 861 / 1230

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 1.00 Mar. 12, 2008 Page 813 of 1178
REJ09B0403-0100
21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR)
TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the transmission descriptor. Which transmission descriptor information is used
for processing by the E-DMAC can be recognized by monitoring addresses displayed in this
register. The address from which the E-DMAC is actually fetching a descriptor may be different
from the value read from this register.
Bit Bit Name
Initial
value
R/W Description
31 to 0 TDFA31 to
TDFA0 All 0 R Transmission-Descriptor Fetch Address
These bits can only be read. Writing is prohibited.
21.2.17 Flow Control FIFO Threshold Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the
threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the
receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The
condition to start the flow control is decided by taking OR operation on the two thresholds.
Therefore, the flow control by the two thresholds is independently started.
When flow control is performed according to the RFD bits setting, if the setting is the same as the
depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when
the remaining FIFO is (FIFO data depth
−
64) bytes. For instance, when RFD in FDR
=
0 and
RFD in FCFTR
=
0, flow control is started when (256
−
64) bytes of data is stored in the receive
FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR.
Bit Bit Name
Initial
value
R/W Description
31 to 19

All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.