Renesas H8S Family, Hardware Manual

Page: 1102 / 1230

Section 27 Clock Pulse Generator
Rev. 1.00 Mar. 12, 2008 Page 1054 of 1178
REJ09B0403-0100
27.2 PLL Multiplier Circuit
The PLL multiplier circuit generates a clock of 4 times the frequency of its input clock. The
frequency range of the multiplied clock is shown in table 27.3.
Table 27.3 Ranges of Multiplied Clock Frequency
Input Clock (MHz) Multiplier System Clock (MHz)
Crystal Resonator, 5 to 8.5 4 20 to 34
External Clock
27.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (
φ
), and generates
φ
/2,
φ
/4,
φ
/8,
φ
/16,
and
φ
/32 clocks.
27.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (
φ
) or medium-speed clock (
φ
/2,
φ
/4,
φ
/8,
φ
/16, or
φ
/32) by the SCK2 to SCK0 bits in
SBYCR.
27.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P56DDR bit in
P5DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
When the subclock is not used, subclock input should not be enabled.
27.6 Subclock Waveform Shaping Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided
φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.