Renesas H8S Family, Hardware Manual

Page: 105 / 1230

Section 2 CPU
Rev. 1.00 Mar. 12, 2008 Page 57 of 1178
REJ09B0403-0100
2.8 Processing States
The H8S/2600 CPU has four main processing states: the reset state, exception handling state,
program execution state and power-down state. Figure 2.13 indicates the state transitions.
•
Reset State
In this state, the CPU and all on-chip peripheral modules are initialized and not operating.
When the
RES
input goes low, all current processing stops and the CPU enters the reset state.
All interrupts are masked in the reset state. Reset exception handling starts when the
RES
signal changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
•
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
•
Program Execution State
In this state, the CPU executes program instructions in sequence.
•
Program Stop State
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters software standby mode. For further
details, refer to section 28, Power-Down Modes.