Renesas H8S Family, Hardware Manual

Page: 808 / 1230

Section 20 Ethernet Controller (EtherC)
Rev. 1.00 Mar. 12, 2008 Page 760 of 1178
REJ09B0403-0100
20.3 Register Description
The EtherC has the following registers. For details on addresses and access sizes of registers, see
section 29, List of Registers.
MAC Layer Interface Control Register
•
EtherC mode register (ECMR)
•
EtherC status register (ECSR)
•
EtherC interrupt permission register (ECSIPR)
•
PHY interface register (PIR)
•
MAC address high register (MAHR)
•
MAC address low register (MALR)
•
Receive frame length register (RFLR)
•
PHY status register (PSR)
•
Transmit retry over counter register (TROCR)
•
Delayed collision detect counter register (CDCR)
•
Lost carrier counter register (LCCR)
•
Carrier not detect counter register (CNDCR)
•
CRC error frame counter register (CEFCR)
•
Frame receive error counter register (FRECR)
•
Too-short frame receive counter register (TSFRCR)
•
Too-long frame receive counter register (TLFRCR)
•
Residual-bit frame counter register (RFCR)
•
Multicast address frame counter register (MAFCR)
•
IPG register (IPGR)
•
Automatic PAUSE frame set register (APR)
•
Manual PAUSE frame set register (MPR)
•
Automatic PAUSE frame retransmission count set register (TPAUSER)