Renesas H8S Family, Hardware Manual

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Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 886 of 1178
REJ09B0403-0100
22.8 DTC Transfer
22.8.1 Overview
DTC transfer can be performed for endpoints 1 and 2 in this module. Note that longword data
cannot be transferred.
When endpoint 1 holds at least one byte of valid receive data, a DTC request for endpoint 1 is
generated. When endpoint 2 holds no valid data, a DTC request for endpoint 2 is generated.
If the DTC transfer is enabled by setting the EP1DMAE bit in the DTC transfer setting register to
1, zero-length data reception at endpoint 1 is ignored. When the DTC transfer is enabled, the
RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG (note that the PKTE bit
must be set to 1 when the transfer data is less than the maximum number of bytes). When all the
data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the maximum
number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters the FULL
state, and the data in the FIFO can be transmitted (see figures 22.20 and 22.21). Since the request
for a DTC transfer end interrupt is not automatically cleared, it should be cleared within the
interrupt processing.