Renesas H8S Family, Hardware Manual

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Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Mar. 12, 2008 Page 505 of 1178
REJ09B0403-0100
Section 15 Serial Communication Interface with FIFO
(SCIF)
This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that
supports asynchronous serial communication.
The SCIF enables asynchronous serial communication with standard asynchronous
communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART). The SCIF
also has independent 16-stage FIFO buffers for transmission and reception to provide efficient
high-speed continuous communication.
In addition, the SCIF can be connected to the LPC interface for direct control from the LPC host.
15.1 Features
•
Full-duplex communication:
The transmitter and receiver are independent, enabling transmission and reception to be
executed simultaneously. Both the transmitter and receiver use 16-stage FIFO buffering,
enabling continuous transmission and continuous reception of serial data.
•
On-chip baud rate generator allows any bit rate to be selected
•
Modem control function
•
Data length: Selectable from 5, 6, 7, and 8 bits
•
Parity: Selectable from even parity, odd parity, and no parity
•
Stop bit length: Selectable from 1, 1.5, and 2 bits
•
Receive error detection: Parity, overrun, and framing errors
•
Break detection