Renesas H8S Family, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 653 of 1178
REJ09B0403-0100
6. The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
cyc
, as shown in
table 18.11. However, because of the rise and fall times, the I
2
C bus interface specifications
may not be satisfied at the maximum transfer rate. Table 18.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.
t
SCLLO
in high-speed mode and t
STASO
in standard mode fail to satisfy the I
2
C bus interface
specifications for worst-case calculations of t
Sr
/t
Sf
. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
2
C
bus.