Renesas H8S Family, Hardware Manual

Page: 708 / 1230

Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 660 of 1178
REJ09B0403-0100
Data transmission
Bit 7
Address reception
SCL
TRS bit
Waveform at problem occurrence
ICDR read and ICCR read/write are disabled
(6 system clock period)
8
R/
W
A
9
The rise of the 9th clock is detected
SDA
ICDR write
Figure 18.33 ICDR Register Read and ICCR Register Access Timing
in Slave Transmit Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
12. Note on TRS bit setting in slave mode
In I
2
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 18.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 18.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 18.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.