Section 17 Synchronous Serial Communication Unit (SSU)
Rev. 1.00 Mar. 12, 2008 Page 555 of 1178
REJ09B0403-0100
Bit Bit
Name
Initial
Value
R/W Description
4
SOL
0
R/W
Serial Data Output Value Select
The serial data output retains its level of the last bit
after completion of transmission. The output level
before or after transmission can be specified by setting
this bit. When specifying the output level, use the MOV
instruction after clearing the SOLP bit to 0. Since writing
to this bit during data transmission causes malfunctions,
this bit should not be changed.
0: Serial data output is changed to low.
1: Serial data output is changed to high.
3
SOLP
1
R/W
SOL Bit Write Protect
When changing the output level of serial data, set the
SOL bit to 1 or clear the SOL bit to 0 after clearing the
SOLP bit to 0 using the MOV instruction.
0: Output level can be changed by the SOL bit
1: Output level cannot be changed by the SOL bit. This
bit is always read as 1.
2
SCKS
0
R/W
SSCK Pin Select
Selects that the SSCK pin functions as a port or a serial
clock pin. When the SSCK pin is used as a serial clock
pin, this bit must be set to 1.
0: Functions as an I/O port.
1: Functions as a serial clock.
1
0
CSS1
CSS0
0
0
R/W
R/W
SCS
Pin Select
Select that the
SCS
pin functions as a port or
SCS
input
or output. However, when MSS
=
0, the
SCS
pin
functions as an input pin regardless of the CSS1 and
CSS0 settings.
00: I/O port
01: Function as
SCS
input
10: Function as
SCS
automatic input/output (function as
SCS
input before and after transfer and output a
low level during transfer)
11: Function as
SCS
automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
Summary of Contents for H8S Family
Page 2: ...Rev 1 00 Mar 12 2008 Page ii of xIviii...
Page 8: ...Rev 1 00 Mar 12 2008 Page viii of xIviii...
Page 28: ...Rev 1 00 Mar 12 2008 Page xxviii of xIviii...
Page 48: ...Rev 1 00 Mar 12 2008 Page xlviii of xIviii...
Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
Page 1226: ...Rev 1 00 Mar 12 2008 Page 1178 of 1178 REJ09B0403 0100...
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Page 1230: ...H8S 2472 Group H8S 2462 Group Hardware Manual...