Renesas H8S Family, Hardware Manual, Page: 739 / 1230

Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 691 of 1178
REJ09B0403-0100
19.3.11 Status Registers 1 to 3 (STR1 to STR3)
The STR registers are 8-bit registers that indicate status information during LPC interface
processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the
slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to
bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0. The functions for
bits 7 to 4 in STR3 differ according to the settings of bit SELSTR3 in HISEL and the TWRE bit in
LADR3L. For details, see section 19.3.18, Host Interface Select Register (HISEL). The registers
selected from the host processor according to the I/O address are described in the following
sections. For information on STR1 and STR2 selection, see section 19.3.6, LPC Channel 1,2
Address Register H, L (LADR12H, LADR12L), and information on STR3 selection, see section
19.3.7, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle,
the data in the selected register is transferred to the host processor.
The STR registers are initialized to H'00 by a reset or in hardware standby mode.
•
STR1
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU17
DBU16
DBU15
DBU14
All 0 R/W R Defined by User
The user can use these bits as necessary.
3 C/
D
1 0 R R Command/Data
When the host processor writes to an IDR1 register,
bit 2 of the I/O address (when CH1OFFSEL1 = 0) or
bit 0 of the I/O address (when CH1OFFSEL1 = 1) is
written to this bit to indicate whether IDR1 contains
data or a command.
0: Content of input data register (IDR1) is data
1: Content of input data register (IDR1) is a
command
2 DBU12 0 R/W R Defined by User
The user can use this bit as necessary.