Renesas H8S Family, Hardware Manual

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Section 14 CRC Operation Circuit (CRC)
Rev. 1.00 Mar. 12, 2008 Page 499 of 1178
REJ09B0403-0100
14.2.2 CRC Data Input Register (CRCDIR)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
The result is obtained in CRCDOR.
14.2.3 CRC Data Output Register (CRCDOR)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the
bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC
operation result is additionally written to the bytes to which CRC operation is to be performed, the
CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in
CRCCR are set to G1 = 0 and G0 = 1, respectively, the lower byte of this register contains the
result.
14.3 CRC Operation Circuit Operation
The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An
example in which a CRC code for hexadecimal data H'F0 is generated using the X
16
+ X
12
+ X
5
+ 1
polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
CRCCR
CRCDORH
CRCDORL
CRCDOR clearing
1. Write H'83 to CRCCR
1
7
0 0 0 0 0
0
7
0
7
0
7
0
1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
CRCDIR
CRCDORH
CRCDORL
CRC code generation
2. Write H'F0 to CRCDIR
1 1 1 1 0 0 0 0
1 1 1 1 0 1 1 1
1 0 0 0 1 1 1 1
CRC code = H'F78F
CRC code
Output
Data
3. Read from CRCDOR
7
7
7 F F F 0 8
7 0 0 0
4. Serial transmission (LSB first)
1 1 1 1 0 1
1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 0 0
0
Figure 14.2 LSB-First Data Transmission