Renesas H8S Family, Hardware Manual

Page: 703 / 1230

Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 655 of 1178
REJ09B0403-0100
2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is
(– 6t
cyc
) (n = 0 to 5).
3. Calculated using the I
2
C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
7. Notes on ICDR register read at end of master reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 18.29 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).