Section 25
Flash Memory
Rev. 1.00 Mar. 12, 2008 Page 993 of 1178
REJ09B0403-0100
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new
bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly
be needed. When two or more selection commands are sent at once, the last command will be
valid.
All of these commands, except for the boot program status inquiry command (H'4F), will be valid
until the boot program receives the programming/erasing transition (H'40). The host can choose
the needed commands out of the commands and inquiries listed above. The boot program status
inquiry command (H'4F) is valid after the boot program has received the programming/erasing
transition command (H'40).
(a)
Supported Device Inquiry
The boot program will return the device codes of supported devices and the product code in
response to the supported device inquiry.
Command H'20
•
Command, H'20, (1 byte): Inquiry regarding supported devices
Response
H'30
Size Number of devices
Number
of
characters
Device code
Product name
···
SUM
•
Response, H'30, (1 byte): Response to the supported device inquiry
•
Size (1 byte): Number of bytes to be transmitted, excluding the command, size, and
checksum, that is, the amount of data contributes by the number of devices, characters, device
codes and product names
•
Number of devices (1 byte): The number of device types supported by the boot program
•
Number of characters (1 byte): The number of characters in the device codes and boot
program’s name
•
Device code (4 bytes): ASCII code of the supporting product
•
Product name (n bytes): Type name of the boot program in ASCII-coded characters
•
SUM (1 byte): Checksum
The checksum is calculated so that the total number of all values from the command byte to
the SUM byte becomes H'00.
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
Page 1226: ...Rev 1 00 Mar 12 2008 Page 1178 of 1178 REJ09B0403 0100...
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