Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 684 of 1178
REJ09B0403-0100
19.3.5
Pin Function Control Register (PINFNCR)
PINFNCR selects whether the pins of the associated port are used for the LPC function or general
I/O.
R/W
Bit Bit
Name
Initial
Value Slave Host
Description
7 to 3
All
0
R/W
Reserved
The initial value bit should not be changed.
2
SERIRQOFF
0 R/W
0: SERIRQ pin
1: General I/O port
1
LPCPDOFF
0 R/W
0: LPCPD pin
1: General I/O port
0
CLKRUNOFF
0 R/W
0: CLKRUN pin
1: General I/O port
19.3.6
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 19.2 shows the initial value of each register. Table 19.3 shows the host register selection in
address match determination. Table 19.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 19.2 LADR1, LADR2 Initial Values
Register Name
Initial Value
Description
LADR1
H'0060
I/O address of channel 1
LADR2
H'0062
I/O address of channel 2
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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