Renesas H8S Family, Hardware Manual

Page: 897 / 1230

Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 849 of 1178
REJ09B0403-0100
22.3.20 FIFO Clear Register (FCLR)
FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit Bit Name
Initial
Value
R/W Description
7

Undefined

Reserved
The initial value should not be changed.
6 EP3 CLR Undefined W EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
5 EP1 CLR Undefined W EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
4 EP2 CLR Undefined W EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
3 to 1

All 0 R Reserved
The initial value should not be changed.
0 EP0i CLR Undefined W EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.