Section 13 Serial Communication Interface (SCI)
Rev. 1.00 Mar. 12, 2008 Page 439 of 1178
REJ09B0403-0100
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Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit Bit
Name
Initial
Value R/W Description
7 TIE
0 R/W
Transmit
Interrupt
Enable
When this bit is set to 1, a TXI interrupt request is enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests are
enabled.
5 TE
0 R/W
Transmit
Enable
When this bit is set to 1, transmission is enabled.
4 RE
0 R/W
Receive
Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the MP
bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
2
TEIE
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1 and 0
These bits control the clock output from the SCK pin. In GSM
mode, clock output can be dynamically switched. For details,
see section 13.7.8, Clock Output Control.
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1x: Reserved
When GM in SMR = 1
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output
[Legend]
x: Don't
care
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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Page 1230: ...H8S 2472 Group H8S 2462 Group Hardware Manual...