Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 888 of 1178
REJ09B0403-0100
22.8.3
DTC Transfer for Endpoint 2
When the transmit data at EP2 is transferred by the DTC, the USB function module automatically
performs the same processing as writing 1 to the PKTE bit in TRG if the currently selected FIFO
(64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not
write 1 to the PKTE bit. To transfer data of less than 64 bytes, the user must write 1 to the PKTE
bit on a DTC transfer end interrupt. If the user writes 1 to the PKTE bit when the maximum
number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed.
To end the DTC transfer, write 0 to the EP2EMPTY bit in IFR0, after clearing the EP2DMAE bit
in DMA to 0 within the processing routine for a DTC transfer end interrupt. If this procedure is
omitted, the DTC transfer end interrupt is not cleared. To perform the DTC transfer again, in
addition to the said procedure, set the number of transfers, set the DTCERF register, and then set
the EP2DMAE bit in DMA to 1.
Figure 22.21 shows an example for transmitting 150 bytes of data to the host. In this case, internal
processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed
twice. This internal processing is performed when the currently selected data FIFO becomes full.
Accordingly, this processing is automatically performed only when 64-byte data is sent.
When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit is not
performed, and the user must write 1 to the PKTE bit by software. In this case, the application has
no more data to transfer but the USB function module continues to output DTC requests for EP2
as long as the FIFO has an empty space. Therefore, when all data has been transferred, write 0 to
the EP2DMAE bit in DMA to cancel DTC transfer requests, and then write 0 to the EP2EMPTY
bit in IFR0 to clear the request for a DTC transfer end interrupt.
PKTE
(Automatically
performed)
PKTE
(Automatically
performed)
PKTE is
not performed
Execute by DMA transfer
end interrupt (user)
64 bytes
64 bytes
22 bytes
Figure 22.21 PKTE Bit Operation for EP2
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
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Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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