Renesas H8S Family, Hardware Manual

Page: 567 / 1230

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Mar. 12, 2008 Page 519 of 1178
REJ09B0403-0100
Bit Bit Name Initial Value R/W Description
5 THRE 1 R FTHR Empty
Indicates that FTHR is ready to accept new data for
transmission.
•
When the FIFO is enabled
0: Transmit data of one or more bytes remains in the
transmit FIFO.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in the transmit FIFO.
[Setting condition]
When the transmit FIFO becomes empty
•
When the FIFO is disabled
0: Transmit data remains in FTHR.
[Clearing condition]
Transmit data is written to FTHR
1: No transmit data in FTHR
[Setting condition]
When data transfer from FTHR to FTSR is
completed
4 BI 0 R Break Interrupt
Indicates detection of the receive data break signal.
When the FIFO is enabled, a break interrupt occurs
in any receive data in the FIFO, and this bit is set
when the receive data is in the first FIFO buffer.
Reception of the next data starts after the input
receive data becomes mark and a valid start bit is
received.
0: Break signal not detected
[Clearing condition]
FLSR read
1: Break signal detected
[Setting condition]
When input receive data stays at space (low level)
for a reception time exceeding the length of one
frame