Section 25 Flash Memory
Rev. 1.00 Mar. 12, 2008 Page 956 of 1178
REJ09B0403-0100
25.4.3
User Program Mode
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be
programmed/erased.)
Programming/erasing is executed by downloading the program in the microcomputer.
The overview flow is shown in figure 25.11.
High voltage is applied to internal flash memory during the programming/erasing processing.
Therefore, transition to reset or hardware standby must not be executed. Doing so may damage or
destroy flash memory. If reset is executed accidentally, reset must be released after the reset input
period of 100
µ
s which is longer than normal.
When programming,
program data is prepared
Programming/erasing
procedure program is
transferred to the on-chip
RAM and executed
Programming/erasing
start
Programming/erasing
end
Make sure that the program data will not overlap the download
destination specified by FTDAR.
The FWE bit is set to 1 by inputting a high level signal to the FWE
pin.
Programming/erasing is executed only in the on-chip RAM.
However, if program data is in a consecutive area and can be
accessed by the MOV.B instruction of the CPU like RAM or
ROM, the program data can be in an external space.
After programming/erasing is finished, input a low level signal to
the FWE pin and transfer to the hardware protection state.
1.
2.
3.
4.
Figure 25.11 Programming/Erasing Overview Flow
Summary of Contents for H8S Family
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Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
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Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
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Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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