Renesas H8S Family, Hardware Manual

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Section 20 Ethernet Controller (EtherC)
Rev. 1.00 Mar. 12, 2008 Page 772 of 1178
REJ09B0403-0100
20.3.13 CRC Error Frame Counter Register (CEFCR)
CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter
value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 CEFC31 to
CEFC0
All 0 R/W CRC Error Frame Count
These bits indicate the count of CRC error frames
received.
20.3.14 Frame Receive Error Counter Register (FRECR)
FRECR is a 32-bit counter that indicates the number of frames input from the PHY-LSI for which
a receive error was indicated by the RM_RX-ER pin. FRECR is incremented each time the
RM_RX-ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count
is halted. The counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 FREC31 to
FREC0
All 0 R/W Frame Receive Error Count
These bits indicate the count of errors during frame
reception.
20.3.15 Too-Short Frame Receive Counter Register (TSFRCR)
TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have
been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The
counter value is cleared to 0 by a write to this register with any value.
Bit Bit Name
Initial
Value
R/W Description
31 to 0 TSFC31 to
TSFC0
All 0 R/W Too-Short Frame Receive Count
These bits indicate the count of frames received with
a length of less than 64 bytes.