Renesas H8S Family, Hardware Manual

Page: 1070 / 1230

Section 26 Boundary Scan (JTAG)
Rev. 1.00 Mar. 12, 2008 Page 1022 of 1178
REJ09B0403-0100
26.3 Register Descriptions
The JTAG has the following registers.
•
Instruction register (SDIR)
•
Bypass register (SDBPR)
•
Boundary scan register (SDBSR)
•
ID code register (SDIDR)
Instructions can be input to the instruction register (SDIR) by serial transfer from the test data
input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass
register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS,
CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 346-bit register in H8S/2472
group, 333-bit register in H8S/2462 group to which the ETDI and ETDO pins are connected in
SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a
fixed code can be output via the ETDO pin in IDCODE mode. All registers cannot be accessed
directly by the CPU.
Table 26.2 shows the kinds of serial transfer possible with each JTAG register.
Table 26.2 JTAG Register Serial Transfer
Register Serial Input Serial Output
SDIR Possible Possible
SDBPR Possible Possible
SDBSR Possible Possible
SDIDR Impossible Possible