Renesas H8S Family, Hardware Manual

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Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Mar. 12, 2008 Page 518 of 1178
REJ09B0403-0100
15.3.11 Line Status Register (FLSR)
FLSR is a read-only register that indicates the status information of data transmission.
Bit Bit Name Initial Value R/W Description
7 RXFIFOERR 0 R Receive FIFO Error
Indicates that at least one data error (parity error,
framing error, or break interrupt) has occurred when
the FIFO is enabled.
0: No receive FIFO error
[Clearing condition]
When FRBR is read or FLSR is read while there is
no remaining data that could cause an error after an
FIFO clear.
1: A receive FIFO error
[Setting condition]
When at least one data error (parity error, framing
error, or break interrupt) has occurred in the FIFO
6 TEMT 1 R Transmitter Empty
Indicates whether transmit data remains.
•
When the FIFO is disabled
0: Transmit data remains in FTHR or FTSR.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in FTHR and FTSR.
[Setting condition]
When no transmit data remains in FTHR and FTSR.
•
When the FIFO is enabled
0: Transmit data remains in the transmit FIFO or
FTSR.
[Clearing condition]
Transmit data is written to FTHR.
1: No transmit data remains in the transmit FIFO and
FTSR.
[Setting condition]
When no transmit data remains in the transmit FIFO
and FTSR