Renesas H8S Family, Hardware Manual

Page: 894 / 1230

Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 846 of 1178
REJ09B0403-0100
22.3.16 EP0o Receive Data Size Register (EPSZ0o)
EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit Bit Name
Initial
Value
R/W Description
7 to 0 — All 0 R Number of receive data for endpoint 0
22.3.17 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received
data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit Bit Name
Initial
Value
R/W Description
7 to 0 — All 0 R Number of received bytes for endpoint 1
22.3.18 Trigger Register (TRG)
TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Bit Bit Name
Initial
Value
R/W Description
7

Undefined

Reserved
The initial value should not be changed.
6 EP3 PKTE Undefined W EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
5 EP1 RDFN Undefined W EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-buffer configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.