Renesas H8S Family, Hardware Manual, Page: 735 / 1230

Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 687 of 1178
REJ09B0403-0100
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
of LADR3 is inverted, and the values of bits 3 to 0 are ignored. When determining an IDR3,
ODR3, or STR3 address match in KCS mode, an SMICFLG, SMICCSR, SMICDTR address
match in SMIC mode, and a BTDTR, BTCR, BTIMSR address match in BT mode, the values of
bits 3 to 0 are ignored.
Register selection according to the bits ignored in address match determination is as shown in the
following table.
I/O Address
Bits 15 to5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Transfer
Cycle Host Register
Selection
Bits 15 to5 Bit 4 Bit 3 0 Bit 1 0 I/O write IDR3 write, C/
D
3
←
0
Bits 15 to5 Bit 4 Bit 3 1 Bit 1 0 I/O write IDR3 write, C/
D
3
←
1
Bits 15 to5 Bit 4 Bit 3 0 Bit 1 0 I/O read ODR3 read
Bits 15 to5 Bit 4 Bit 3 1 Bit 1 0 I/O read STR3 read
Bits 15 to5
Bit 4
0 0 0 0 I/O write TWR0MW write
Bits 15 to5
Bit 4
0 0 0 1 I/O write TWR1 to TWR15
write
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1
Bits 15 to5
Bit 4
0 0 0 0 I/O read TWR0SW read
Bits 15 to5
Bit 4
0 0 0 1 I/O read TWR1 to TWR15
read
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1