Renesas H8S Family, Hardware Manual

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Section 6 Bus Controller (BSC)
Rev. 1.00 Mar. 12, 2008 Page 152 of 1178
REJ09B0403-0100
6.6 Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM
bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four
or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected
for burst ROM access.
6.6.1 Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.30 and 6.31.
T
1
Address bus
φ
AS
/
IOS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changes
Read data Read data Read data
(IOSE = 0)
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)