Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 856 of 1178
REJ09B0403-0100
22.3.25 Endpoint Information Register (EPIR)
This register sets the information for each endpoint. Each endpoint needs five bytes to store the
information. Writing data should be done in sequence starting at logical endpoint 0. Do not write
data of more than 50 bytes (five bytes multiplied by ten endpoints) to this register. The
information should be written to this register only once at a power-on reset and no data should be
written after that. Description of writing data for one endpoint is shown below.
Although this register consists of one register to which data is written sequentially for one address,
the write data for the endpoint 0 is described as EPIR00 to EPIR05 (EPIR endpoint number in
write order) to make the explanation understood easier. Write should start at EPIR00.
•
EPIR00
Bit Bit
Name
Initial
Value
R/W Description
7 to 4
D7 to D4
Undefined W
Endpoint Number
[Enable setting range]
0 to 3
3, 2
D3, D2
Undefined W
Endpoint Configuration Number
[Enable setting range]
0 or 1
1, 0
D1, D0
Undefined W
Endpoint Interface Number
[Enable setting range]
0 to 3
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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