Renesas H8S Family, Hardware Manual

Page: 683 / 1230

Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 635 of 1178
REJ09B0403-0100
SDA
(master output)
SDA
(slave output)
2 1 2 1 4 3 6 5 8 7 9
Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
Address
+R/
W
Address
+R/
W
Undefined value
[8] IRIC clear [10] ICDR read (dummy read)
User processing
2 1 2 1 4 3 6 5 8 7 9
SCL
(Pin waveform)
Start condition generation
Slave address
Data 1
[6]
A
R/
W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)
SDA
(master output)
SDA
(slave output)
2 1 4 3 6 5 8 7 9 8 9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0
IRIC
ICDRS
ICDRF
ICDRR
Data (n-1)
SCL
(master output)
SCL
(slave output)
[8] IRIC clear
[12] IRIC clear
[9] Set ACKB=1
[10] ICDR read (Data (n-1)) [10] ICDR read
(Data (n))
User processing
Data (n)
Data (n-1)
Data (n-2)
[6] [6]
[11]
A A
Stop condition generation
[7] SCL is fixed low until ICDR is read [7] SCL is fixed low until ICDR is read
Data (n-1)
Data (n)
Data (n)
[8] IRIC clear
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)