Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 732 of 1178
REJ09B0403-0100
19.3.32 BT FIFO Valid Size Register 0 (BTFVSR0)
BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data
size in the FIFO for host write transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to
0
N7 to N0 All 0
R
These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the slave can read)
for host write transfer. When data is written from the
host, the value in BTFVSR0 is incremented by the
number of bytes that have been written to. Further,
when data is read from the slave, the value is
decremented by only the number of bytes that have
been read.
19.3.33 BT FIFO Valid Size Register 1 (BTFVSR1)
BTFVSR1 is one of the registers used to implement BT mode. BTFVSR1 indicates a valid data
size in the FIFO for host read transfer.
R/W
Bit
Bit Name Initial Value Slave Host Description
7 to 0 N7 to N0 All 0
R
These bits indicate the number of valid bytes in the
FIFO (the number of bytes which the host can read)
for host read transfer. When data is written from the
slave, the value in BTFVSR1 is incremented by the
number of bytes that have been written to. Further,
when data is read from the host, the value is
decremented by only the number of bytes that have
been read.
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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Page 1230: ...H8S 2472 Group H8S 2462 Group Hardware Manual...