Renesas H8S Family Hardware Manual Download

Page: 19 / 1230

Rev. 1.00 Mar. 12, 2008 Page xix of xIviii

17.3.7

SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 562

17.3.8

SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) .................................... 563

17.3.9

SS Shift Register (SSTRSR) ................................................................................. 563

17.4

Operation ........................................................................................................................... 564

17.4.1

Transfer Clock ...................................................................................................... 564

17.4.2

Relationship of Clock Phase, Polarity, and Data .................................................. 564

17.4.3

Relationship between Data Input/Output Pins and Shift Register ........................ 565

17.4.4

Communication Modes and Pin Functions ........................................................... 566

17.4.5

SSU Mode............................................................................................................. 568

17.4.6

SCS

Pin Control and Conflict Error...................................................................... 576

17.4.7

Clock Synchronous Communication Mode .......................................................... 577

17.5

Interrupt Requests .............................................................................................................. 583

17.6

Usage Note......................................................................................................................... 583

17.6.1

Setting of Module Stop Mode............................................................................... 583

Section 18 I

C Bus Interface (IIC) .....................................................................585

18.1

Features.............................................................................................................................. 585

18.2

Input/Output Pins ............................................................................................................... 588

18.3

Register Descriptions ......................................................................................................... 589

18.3.1

C Bus Data Register (ICDR) .............................................................................. 589

18.3.2

Slave Address Register (SAR).............................................................................. 590

18.3.3

Second Slave Address Register (SARX) .............................................................. 591

18.3.4

C Bus Mode Register (ICMR)............................................................................ 593

18.3.5

C Bus Transfer Rate Select Register (IICX3)..................................................... 595

18.3.6

C Bus Control Register (ICCR).......................................................................... 598

18.3.7

C Bus Status Register (ICSR)............................................................................. 607

18.3.8

C Bus Extended Control Register (ICXR).......................................................... 611

18.3.9

C SMBus Control Register (ICSMBCR)............................................................ 615

18.4

Operation ........................................................................................................................... 617

18.4.1

C Bus Data Format ............................................................................................. 617

18.4.2

Initialization .......................................................................................................... 619

18.4.3

Master Transmit Operation ................................................................................... 619

18.4.4

Master Receive Operation..................................................................................... 623

18.4.5

Slave Receive Operation....................................................................................... 632

18.4.6

Slave Transmit Operation ..................................................................................... 640

18.4.7

IRIC Setting Timing and SCL Control ................................................................. 643

18.4.8

Operation Using the DTC ..................................................................................... 646

18.4.9

Noise Canceler...................................................................................................... 648

18.4.10

Initialization of Internal State ............................................................................... 648

18.5

Interrupt Source ................................................................................................................. 650

Summary of Contents for H8S Family

Page 1: ...evision Date Mar 12 2008 16 Renesas 16 Bit Single Chip Microcomputer H8S Family H8S 2400 Series H8S 2472 R4F2472 H8S 2462 R4F2462 Rev 1 00 REJ09B0403 0100 H8S 2472 Group H8S 2462 Group Hardware Manual...

Page 2: ...Rev 1 00 Mar 12 2008 Page ii of xIviii...

Page 3: ...ity and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transm...

Page 4: ...tialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input o...

Page 5: ...g items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes...

Page 6: ...are Manual for a detailed description of the instruction set Notes on reading this manual In order to understand the overall functions of the chip Read the manual according to the contents This manual...

Page 7: ...Series H8S 2000 Series Software Manual REJ09B0139 User s manuals for development tools Document Title Document No H8S H8 300 Series C C Compiler Assembler Optimizing Linkage Editor User s Manual REJ1...

Page 8: ...Rev 1 00 Mar 12 2008 Page viii of xIviii...

Page 9: ...Registers 32 2 4 2 Program Counter PC 33 2 4 3 Extended Control Register EXR 33 2 4 4 Condition Code Register CCR 34 2 4 5 Multiply Accumulate Register MAC 35 2 4 6 Initial Values of CPU Registers 35...

Page 10: ...Handling 69 4 1 Exception Handling Types and Priority 69 4 2 Exception Sources and Exception Vector Table 70 4 3 Reset 72 4 3 1 Reset Exception Handling 72 4 3 2 Interrupts after Reset 73 4 3 3 On Ch...

Page 11: ...gisters ISR16 ISR 103 Section 6 Bus Controller BSC 105 6 1 Features 105 6 2 Input Output Pins 108 6 3 Register Descriptions 109 6 3 1 Bus Control Register BCR 109 6 3 2 Bus Control Register 2 BCR2 111...

Page 12: ...d Comparator Control Register KBCOMP 166 7 2 10 Event Counter Control Register ECCR 167 7 2 11 Event Counter Status Register ECS 168 7 3 DTC Event Counter 169 7 3 1 Event Counter Handling Priority 170...

Page 13: ...229 8 1 9 Port 9 234 8 1 10 Port A 238 8 1 11 Port B 246 8 1 12 Port C 252 8 1 13 Port D 257 8 1 14 Port E 262 8 1 15 Port F 266 8 2 I O Ports for the H8S 2462 Group 270 8 2 1 Port 1 275 8 2 2 Port 2...

Page 14: ...isters AR and AF OCRAR and OCRAF 376 10 2 4 Timer Interrupt Enable Register TIER 377 10 2 5 Timer Control Status Register TCSR 378 10 2 6 Timer Control Register TCR 379 10 2 7 Timer Output Compare Con...

Page 15: ...nd Counter Clear 408 11 6 2 Conflict between TCNT Write and Increment 409 11 6 3 Conflict between TCOR Write and Compare Match 410 11 6 4 Switching of Internal Clocks and TCNT Operation 411 11 6 5 Mod...

Page 16: ...smission Asynchronous Mode 454 13 4 6 Serial Data Reception Asynchronous Mode 456 13 5 Multiprocessor Communication Function 460 13 5 1 Multiprocessor Serial Data Transmission 462 13 5 2 Multiprocesso...

Page 17: ...escriptions 498 14 2 1 CRC Control Register CRCCR 498 14 2 2 CRC Data Input Register CRCDIR 499 14 2 3 CRC Data Output Register CRCDOR 499 14 3 CRC Operation Circuit Operation 499 14 4 Note on CRC Ope...

Page 18: ...SMR1 544 16 4 Operation of Serial Pin Multiplexed Modes 545 16 4 1 Serial Pin Multiplexed Mode 0 Default SMR0 Register bits SM2 SM1 SM0 0 0 0 545 16 4 2 Serial Pin Multiplexed Mode 1 SMR0 Register bi...

Page 19: ...Features 585 18 2 Input Output Pins 588 18 3 Register Descriptions 589 18 3 1 I2 C Bus Data Register ICDR 589 18 3 2 Slave Address Register SAR 590 18 3 3 Second Slave Address Register SARX 591 18 3 4...

Page 20: ...12 SERIRQ Control Register 0 SIRQCR0 699 19 3 13 SERIRQ Control Register 1 SIRQCR1 703 19 3 14 SERIRQ Control Register 2 SIRQCR2 707 19 3 15 SERIRQ Control Register 3 SIRQCR3 708 19 3 16 SERIRQ Contr...

Page 21: ...Register ECMR 761 20 3 2 EtherC Status Register ECSR 764 20 3 3 EtherC Interrupt Permission Register ECSIPR 766 20 3 4 PHY Interface Register PIR 767 20 3 5 MAC Address High Register MAHR 768 20 3 6 M...

Page 22: ...795 21 2 3 E DMAC Receive Request Register EDRRR 796 21 2 4 Transmit Descriptor List Address Register TDLAR 797 21 2 5 Receive Descriptor List Address Register RDLAR 797 21 2 6 EtherC E DMAC Status R...

Page 23: ...IER2 843 22 3 10 EP0i Data Register EPDR0i 843 22 3 11 EP0o Data Register EPDR0o 844 22 3 12 EP0s Data Register EPDR0s 844 22 3 13 EP1 Data Register EPDR1 845 22 3 14 EP2 Data Register EPDR2 845 22 3...

Page 24: ...22 9 Example of USB External Circuitry 890 22 10 Usage Notes 892 22 10 1 Receiving Setup Data 892 22 10 2 Clearing the FIFO 892 22 10 3 Overreading and Overwriting the Data Registers 892 22 10 4 Assig...

Page 25: ...1 25 1 5 Programming Erasing Interface 923 25 2 Input Output Pins 925 25 3 Register Descriptions 926 25 3 1 Programming Erasing Interface Register 928 25 3 2 Programming Erasing Interface Parameter 93...

Page 26: ...Medium Speed Clock Divider 1054 27 4 Bus Master Clock Select Circuit 1054 27 5 Subclock Input Circuit 1054 27 6 Subclock Waveform Shaping Circuit 1054 27 7 Clock Select Circuit 1055 27 8 Usage Notes...

Page 27: ...ng Mode 1106 Section 30 Platform Environment Control Interface PECI 1119 Section 31 Electrical Characteristics 1121 31 1 Absolute Maximum Ratings 1121 31 2 DC Characteristics 1122 31 3 AC Characterist...

Page 28: ...Rev 1 00 Mar 12 2008 Page xxviii of xIviii...

Page 29: ...2 Branch Address Specification in Memory Indirect Mode 54 Figure 2 13 State Transitions 58 Section 3 MCU Operating Modes Figure 3 1 Address Map 67 Section 4 Exception Handling Figure 4 1 Reset Sequenc...

Page 30: ...ming for 8 Bit 3 State Access Space 141 Figure 6 19 Bus Timing for 16 Bit 2 State Access Space 1 Even Byte Access 142 Figure 6 20 Bus Timing for 16 Bit 2 State Access Space 2 Even Byte Access 143 Figu...

Page 31: ...8 12 Noise Canceler Operation 334 Section 9 14 Bit PWM Timer PWMX Figure 9 1 PWMX D A Block Diagram 357 Figure 9 2 PWMX D A Operation 365 Figure 9 3 Output Waveform OS 0 DADR corresponds to TL 368 Fig...

Page 32: ...e 12 6 Writing to TCNT and TCSR WDT_0 425 Figure 12 7 Conflict between TCNT Write and Increment 426 Figure 12 8 Sample Circuit for Resetting the System by the RESO Signal 427 Section 13 Serial Communi...

Page 33: ...quency is 372 Times the Bit Rate 479 Figure 13 26 Data Re transfer Operation in SCI Transmission Mode 481 Figure 13 27 TEND Flag Set Timings during Transmission 481 Figure 13 28 Sample Transmission Fl...

Page 34: ...Multiplexed Mode 4 549 Section 17 Synchronous Serial Communication Unit SSU Figure 17 1 Block Diagram of SSU 552 Figure 17 2 Relationship of Clock Phase Polarity and Data 564 Figure 17 3 Relationship...

Page 35: ...DS 1 626 Figure 18 13 Sample Flowchart for Operations in Master Receive Mode receiving multiple bytes WAIT 1 627 Figure 18 14 Sample Flowchart for Operations in Master Receive Mode receiving a single...

Page 36: ...ming 747 Figure 19 11 Clock Start Request Timing 749 Figure 19 12 HIRQ Flowchart Example of Channel 1 753 Section 20 Ethernet Controller EtherC Figure 20 1 Configuration of EtherC 758 Figure 20 2 Ethe...

Page 37: ...Figure 22 13 Status Stage Control In Operation 876 Figure 22 14 Status Stage Control Out Operation 877 Figure 22 15 EP1 Bulk Out Transfer Operation 878 Figure 22 16 EP2 Bulk In Transfer Operation 879...

Page 38: ...15 Repeating Procedure of Erasing and Programming 965 Figure 25 16 Procedure for Programming User MAT in User Boot Mode 968 Figure 25 17 Procedure for Erasing User MAT in User Boot Mode 970 Figure 25...

Page 39: ...11 Interrupt Input Timing 1133 Figure 31 12 Basic Bus Timing 2 State Access 1135 Figure 31 13 Basic Bus Timing 3 State Access 1136 Figure 31 14 Basic Bus Timing 3 State Access with One Wait State 113...

Page 40: ...r is Detected 1156 Figure 31 38 MDIO Input Timing 1157 Figure 31 39 MDIO Output Timing 1157 Figure 31 40 WOL Output Timing 1157 Figure 31 41 Data Signal Timing 1159 Figure 31 42 Load Condition 1159 Fi...

Page 41: ...able 2 12 Absolute Address Access Ranges 53 Table 2 13 Effective Address Calculation 1 55 Table 2 13 Effective Address Calculation 2 56 Section 3 MCU Operating Modes Table 3 1 MCU Operating Mode Selec...

Page 42: ...byte Extended Area Multiplex Bus Interface Data Cycle 123 Table 6 12 Address Range for IOS Signal Output 124 Table 6 13 Data Buses Used and Valid Strobes 127 Table 6 14 Data Buses Used and Valid Strob...

Page 43: ...t to TCNT and Count Condition TMR_0 397 Table 11 1 2 Clock Input to TCNT and Count Condition TMR_1 398 Table 11 1 3 Clock Input to TCNT and Count Condition TMR_X TMR_Y 398 Table 11 2 Registers Accessi...

Page 44: ...539 Section 16 Serial Pin Multiplexed Modes Table 16 1 Pin Configuration 542 Section 17 Synchronous Serial Communication Unit SSU Table 17 1 Pin Configuration 553 Table 17 2 Communication Modes and Pi...

Page 45: ...t Address Example 755 Section 20 Ethernet Controller EtherC Table 20 1 Pin Configuration 759 Section 22 Ethernet Controller EtherC Table 22 1 Pin Configuration 834 Table 22 2 Example of Limitations fo...

Page 46: ...or Code 1015 Section 26 Boundary Scan JTAG Table 26 1 Pin Configuration 1021 Table 26 2 JTAG Register Serial Transfer 1022 Table 26 3 Correspondence between Pins and Boundary Scan Register H8S 2472 Gr...

Page 47: ...Bus Timing 1152 Table 31 13 LPC Module Timing 1153 Table 31 14 Ethernet Controller Signal Timing 1155 Table 31 15 USB Characteristics when On Chip USB Transceiver is Used USD USD pin characteristics 1...

Page 48: ...Rev 1 00 Mar 12 2008 Page xlviii of xIviii...

Page 49: ...RT 8 bit timer TMR Watchdog timer WDT Asynchronous or synchronous serial communication interface SCI CRC operation circuit CRC Serial communication interface with FIFO SCIF Synchronous serial communic...

Page 50: ...403 0100 Reprogramming count 1000 times Tpy General I O ports I O pins 110 for 176 pin 106 for 144 pin Input only pins 9 Supports various power down states Compact package Package code Body Size Pin P...

Page 51: ...ort 9 Port 8 A D converter Interrupt controller CRC calculator Legend CPU Central processing unit DTC Data transfer controller EVC Event counter SCI Serial communication interface SCIF Serial communic...

Page 52: ...rVSS ETDO PF2 VSS P25 P17 VSS PB7 PB5 P85 P86 P87 VSS UXSEL VCC UEXTAL UXTAL PE7 NC NC P80 PEVref PECI P53 P52 PD5 PD4 PD6 PD7 P30 P31 P33 P32 PD2 PD1 PD3 PD0 PB3 PB1 PB0 VCC PE0 VCC PE1 PE2 P34 P35 P...

Page 53: ...VCC P77 AN7 P76 AN6 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 AVSS PD0 LSCI PD1 LSMI PD2 PME PD3 GA20 PD4 CLKRUN PD5 LPCPD PD6 SCL5 PD7 SDA5 PE0 LAD0 PE1 LAD1 PE2 LAD2 PE3 LAD3 PE4 LFRAME PE5 LR...

Page 54: ...6 IRQ6 RS6 DB6 HC6 FA14 C02 4 P47 IRQ7 RS7 DB7 HC7 A15 AD15 P47 IRQ7 RS7 DB7 HC7 FA15 D03 5 P56 EXCL phi P56 EXCL phi NC C01 6 WR HWR P57 NC D02 7 VSS VSS VSS E04 8 RES RES RES D01 9 MD1 MD1 VSS E03 1...

Page 55: ...2 PC1 SDA2 NC M01 NC NC NC M02 32 PC0 SCL2 PC0 SCL2 NC M03 33 PA7 ExIRQ7 EVENT7 EXOUT A23 PA7 ExIRQ7 EVENT7 EXOUT VCC N01 34 PA6 ExIRQ6 EVENT6 LNKSTA A22 PA6 ExIRQ6 EVENT6 LNKSTA VCC M04 35 PA5 ExIRQ5...

Page 56: ...48 P82 SCL1 P82 SCL1 NC P06 49 P81 SDA0 P81 SDA0 NC M07 50 P80 SCL0 P80 SCL0 NC N07 NC NC NC R07 51 PE7 SERIRQ PE7 SERIRQ NC P07 NC NC NC M08 52 PE6 LCLK PE6 LCLK NC N08 53 PE5 LRESET PE5 LRESET NC R0...

Page 57: ...6 AN6 P76 AN6 NC N13 75 P77 AN7 P77 AN7 NC P15 76 AVCC AVCC VCC N14 77 AVref AVref VCC M13 78 P60 IRQ14 PWX0 D0 P60 IRQ14 PWX0 NC N15 79 P61 IRQ15 PWX1 D1 P61 IRQ15 PWX1 NC M14 80 P62 PWX2 D2 P62 PWX2...

Page 58: ...94 VSS VSS VSS F15 95 P27 DTR P27 DTR NC F14 96 P26 DSR P26 DSR NC E13 97 P25 RI P25 RI NC E15 98 P24 DCD P24 DCD NC E14 99 P23 A11 AD11 P23 FA11 E12 100 P22 A10 AD10 P22 FA10 D15 101 P21 A9 AD9 P21 O...

Page 59: ...120 VCC VCC VCC D10 121 D8 P30 ExDB0 FO0 C10 122 D9 P31 ExDB1 FO1 A10 123 D10 P32 ExDB2 FO2 B10 124 D11 P33 ExDB3 FO3 D09 125 D12 P34 ExDB4 FO4 C09 126 D13 P35 ExDB5 FO5 A09 127 D14 P36 ExDB6 FO6 B09...

Page 60: ...ode EXPE 1 Single Chip Mode EXPE 0 Flash Memory Programmer Mode A05 UXTAL UXTAL NC B05 UEXTAL UEXTAL NC D05 UXSEL UXSEL NC A04 PF5 RS13 PF5 RS13 NC B04 PF4 RS12 PF4 RS12 NC C04 NC NC NC A03 141 VSS VS...

Page 61: ...ut EXTAL B2 144 Input For connection to a crystal resonator An external clock can be supplied from the EXTAL pin For an example of crystal resonator connection see section 27 Clock Pulse Generator UXT...

Page 62: ...2 140 99 to 109 111 Output Address output pins D15 to D8 B9 A9 C9 D9 B10 A10 C10 D10 128 to 121 Upper 8 bits of bidirectional bus Data bus D7 to D0 B8 A8 C8 D8 L12 M14 N15 M13 132 to 129 81 to 78 Inpu...

Page 63: ...able interrupts Either IRQn or ExIRQn can be selected as the IRQn interrupt signal input pin WAIT G3 17 Input Requests wait state insertion to bus cycles when an external tri state address space is ac...

Page 64: ...H13 88 Output ETDI H15 89 Input Boundary scan ETCK H14 90 Input Boundary scan interface pins 14 bit PWM timer PWMX PWX0 to PWX3 ExPWX0 to ExPWX2 M13 N15 M14 L12 H3 H4 E3 78 to 81 21 20 10 Output PWM D...

Page 65: ...rface IIC SDA0 to SDA5 P6 N6 L4 K2 K3 M10 49 47 31 29 27 59 Input Output IIC data input output pins These pins can drive a bus directly with the NMOS open drain output AN7 to AN0 N13 R15 P14 R14 P13 M...

Page 66: ...GATE A20 control signal output pin also used as the input pin for monitoring the output state CLKRUN P10 62 Input Output Input output pin used to request starting the LCLK operation while LCLK is sto...

Page 67: ...P3 R3 112 to 119 33 to 35 37 to 41 Input Event counter input pins E3 10 A4 B4 D4 G13 Retain state output pins RS14 RS13 to RS10 RS9 to RS0 G15 G14 C2 B1 C3 B6 B8 A8 C8 D8 92 93 4 to 2 140 132 to 129...

Page 68: ...put Output 8 bit input output pins P47 to P40 C2 B1 C3 B6 B8 A8 C8 D8 4 to 2 140 132 to 129 Input Output 8 bit input output pins P57 to P50 C1 D3 A6 C6 B7 A7 F2 G4 6 5 139 138 136 135 15 16 Input Outp...

Page 69: ...1 112 to 119 Input Output 8 bit input output pins PC7 to PC0 J2 K4 K3 K1 K2 L1 L4 M2 25 to 32 Input Output 8 bit input output pins PD7 to PD0 M10 N10 R10 P10 N11 R11 P11 M11 59 to 66 Input Output 8 bi...

Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...

Page 71: ...register architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Mult...

Page 72: ...hown below Register configuration The MAC register is supported by the H8S 2600 CPU only Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported by the H8S 2600 CPU only The...

Page 73: ...Signed multiply and divide instructions have been added A multiply and accumulate instruction has been added Two bit shift instructions have been added Instructions for saving and restoring multiple r...

Page 74: ...e used Only the lower 16 bits of effective addresses EA are valid Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H 0000 is allocated to the excepti...

Page 75: ...tion vector 3 Exception vector 5 Exception vector 6 Exception vector table Exception vector 4 Figure 2 1 Exception Vector Table Normal Mode PC 16 bits EXR 1 Reserved 1 3 CCR CCR 3 PC 16 bits SP SP SP...

Page 76: ...ndirect Branch Addresses In advanced mode the top area starting at H 00000000 is allocated to the exception vector table in units of 32 bits In each 32 bits the upper 8 bits are ignored and a branch a...

Page 77: ...e that the first part of this range is also used for the exception vector table Stack Structure In advanced mode when the program counter PC is pushed onto the stack in a subroutine call and the PC co...

Page 78: ...ss space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product re...

Page 79: ...ACH MACL MAC 23 63 32 41 31 0 0 15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extende...

Page 80: ...7 These registers are functionally equivalent providing a maximum of sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit gene...

Page 81: ...bit register that manipulates the LDC STC ANDC ORC and XORC instructions When these instructions except for the STC instruction are executed all interrupts including NMI will be masked for three state...

Page 82: ...rrupt Mask Bit Can be read or written by software using the LDC STC ANDC ORC and XORC instructions This bit cannot be used as an interrupt mask bit in this LSI 5 H Undefined R W Half Carry Flag When t...

Page 83: ...ulation instructions 2 4 5 Multiply Accumulate Register MAC This 64 bit register stores the results of multiply and accumulate operations It consists of two 32 bit registers denoted MACH and MACL The...

Page 84: ...djust instructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care...

Page 85: ...LSB En Rn ERn En Rn RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Format R...

Page 86: ...ress an address error does not occur however the least significant bit of the address is regarded as 0 so access begins the preceding address This also applies to instruction fetches When ER7 is used...

Page 87: ...C STMAC CLRMAC Logic operations AND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 1...

Page 88: ...register MAC Multiply accumulate register 32 bit register EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in...

Page 89: ...LSI MOVTPE B Cannot be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general...

Page 90: ...2 Byte operands can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd...

Page 91: ...a 32 bit register to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register...

Page 92: ...ata NOT B W L Rd Rd Takes the one s complement logical complement of general register contents Note Refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Fu...

Page 93: ...fied bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND...

Page 94: ...umber is specified by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a s...

Page 95: ...er false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus...

Page 96: ...e performed between them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size...

Page 97: ...V W if R4L 0 then Repeat ER5 ER6 R4L 1 R4L Until R4L 0 else next if R4 0 then Repeat ER5 ER6 R4 1 R4 Until R4 0 else next Transfers a data block Starting from the address set in ER5 transfers data for...

Page 98: ...Some instructions have two operation fields Register Field Specifies a general register Address registers are specified by 3 bits and data registers by 3 bits or 4 bits Some instructions have two reg...

Page 99: ...Addressing Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 16 ERn d 32 ERn 4 Register indirect with post increment Register indirect with pre decrement...

Page 100: ...with pre decrement ERn The value 1 2 or 4 is subtracted from an address register ERn specified by the register field in the instruction code and the result is the address of a memory operand The resu...

Page 101: ...ion instructions contain 3 bit immediate data in the instruction code specifying a bit number The TRAPA instruction contains 2 bit immediate data in its instruction code specifying a vector address 2...

Page 102: ...is a longword operand the first byte of which is assumed to be 0 H 00 Note that the first part of the address range is also the exception vector area For further details refer to section 4 Exception H...

Page 103: ...ement d 16 ERn or d 32 ERn 4 r op disp r op rm op rn 31 0 31 0 r op Don t care 31 23 31 0 Don t care 31 0 disp 31 0 31 0 31 23 31 0 Don t care 31 23 31 0 Don t care 24 24 24 24 Addressing Mode and Ins...

Page 104: ...Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d 8 PC d 16 PC Memor...

Page 105: ...r to section 4 Exception Handling The reset state can also be entered by a watchdog timer overflow Exception Handling State The exception handling state is a transient state that occurs when the CPU a...

Page 106: ...any state except hardware standby mode a transition to the reset state occurs whenever RES goes low A transition can also be made to the reset state when the watchdog timer overflows From any state a...

Page 107: ...byte units and write data in byte units after bit operation Therefore attention must be paid when these instructions are used for ports or registers including write only bits Instruction BCLR can be u...

Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...

Page 109: ...ion Table 3 1 MCU Operating Mode Selection MCU Operating Mode MD2 MD1 CPU Operating Mode Description 2 1 1 Advanced Extended mode with on chip ROM Single chip mode Mode 2 is single chip mode after a r...

Page 110: ...set an operating mode and to monitor the current operating mode Bit Bit Name Initial Value R W Description 7 EXPE 0 R W Extended Mode Enable Specifies extended mode 0 Single chip mode 1 Extended mode...

Page 111: ...e 0 P97 WAIT pin WAIT pin function is selected by the settings of WSCR and WSCR2 1 CS256 pin Outputs low when a 256 kbyte expansion area of addresses H F80000 to H FBFFFF is accessed 6 IOSE 0 R W IOS...

Page 112: ...ing edge of NMI input 1 0 R W Reserved The initial value should not be changed 0 RAME 1 R W RAM Enable Enables or disables on chip RAM The RAME bit is initialized when the reset state is released 0 On...

Page 113: ...BCR2 WSCR2 PCSR SYSCR2 0 Area from H FFFE88 to H FFFE8F is reserved Control registers of power down states and on chip peripheral modules are accessed in an area from H FFFF80 to H FFFF87 1 Control re...

Page 114: ...tting 1 to the corresponding port data direction register DDR Port 3 functions as a data bus port and parts of port 9 and port C carry bus control signals Ports 4 P43 to P40 and 6 P63 to P60 function...

Page 115: ...FFEFFF H FFE080 H FFFEFF H FFFE40 H FFFF7F H FFFF80 H FFFF00 On chip RAM 128 bytes H FFFFFF Reserved area Reserved area On chip RAM 36 Kbytes External address space On chip RAM 3 968 bytes Internal I...

Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...

Page 117: ...Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low to high transition of the RES pin or when the watchdog timer overflows Illegal instruction Started by exe...

Page 118: ...legal instruction 4 H 000010 to H 000013 Reserved for system use 5 H 000014 to H 000017 6 H 000018 to H 00001B External interrupt NMI 7 H 00001C to H 00001F 8 H 000020 to H 000023 9 H 000024 to H 0000...

Page 119: ...H 0000DC to H 0000DF IRQ8 56 H 0000E0 to H 0000E3 IRQ9 57 H 0000E4 to H 0000E7 IRQ10 58 H 0000E8 to H 0000EB IRQ11 59 H 0000EC to H 0000EF IRQ12 60 H 0000F0 to H 0000F3 IRQ13 61 H 0000F4 to H 0000F7 I...

Page 120: ...e registers of on chip peripheral modules The chip can also be reset by overflow of the watchdog timer For details see section 12 Watchdog Timer WDT 4 3 1 Reset Exception Handling When the RES pin goe...

Page 121: ...e stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Sinc...

Page 122: ...s 4 5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed Trap instruction exception handling can be executed at all times in the progra...

Page 123: ...1178 REJ09B0403 0100 4 6 Stack Status after Exception Handling Figure 4 2 shows the stack after completion of trap instruction exception handling and interrupt exception handling Advanced mode CCR PC...

Page 124: ...e following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 3 shows an example of what happens when th...

Page 125: ...evel interrupt mask control By means of the interrupt control mode I and UI bits in CCR and ICR 3 level interrupt mask control is performed Independent vector addresses All interrupt sources are assig...

Page 126: ...ster IRQ enable register IRQ status register System control register Legend Figure 5 1 Block Diagram of Interrupt Controller 5 2 Input Output Pins Table 5 1 summarizes the pins of the interrupt contro...

Page 127: ...ak control register ABRKCR Break address registers A to C BARA to BARC IRQ sense control registers ISCR16H ISCR16L ISCRH and ISCRL IRQ enable registers IER16 and IER IRQ status registers ISR16 and ISR...

Page 128: ...should always be 0 5 3 2 Address Break Control Register ABRKCR ABRKCR controls the address breaks When both the CMF flag and BIE flag are set to 1 an address break is requested Bit Bit Name Initial Va...

Page 129: ...scription 7 to 0 A23 to A16 All 0 R W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus BARB Bit Bit Name Initial Value R W Description 7 to 0 A15 to A8 A...

Page 130: ...ng edge of IRQn or ExIRQn input 10 Interrupt request generated at rising edge of IRQn or ExIRQn input 11 Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input n 15 to 12...

Page 131: ...IRQn input 11 Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input n 7 to 4 Note IRQn stands for IRQ7 to IRQ4 ISCRL Bit Bit Name Initial Value R W Description 7 6 IRQ3S...

Page 132: ...disabling of interrupt requests IRQ15 to IRQ0 IER16 Bit Bit Name Initial Value R W Description 7 to 0 IRQ15E to IRQ8E All 0 R W IRQn Enable n 15 to 8 The IRQn interrupt request is enabled when this bi...

Page 133: ...level detection is set and IRQn or ExIRQn input is high When IRQn interrupt exception handling is executed when falling edge rising edge or both edge detection is set n 15 to 8 Note IRQn stands for I...

Page 134: ...ExIRQ0 Interrupts IRQ15 to IRQ0 have the following features The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address Using ISCR it is possi...

Page 135: ...features For each on chip peripheral module there are flags that indicate the interrupt request status and enable bits that individually select enabling or disabling of these interrupts When the enabl...

Page 136: ...are set to interrupt control level 0 no priority Table 5 3 Interrupt Sources Vector Addresses and Interrupt Priorities Vector Address Origin of Interrupt Source Name Vector Number Advanced Mode ICR P...

Page 137: ...ICRB1 IIC_2 IICI2 76 H 000130 ICRC2 IIC_3 IICI3 78 H 000138 SCI_3 ERI3 Reception error 3 RXI3 Reception completion 3 TXI3 Transmission data empty 3 TEI3 Transmission end 3 80 81 82 83 H 000140 H 00014...

Page 138: ...nterrupt Source Name Vector Number Advanced Mode ICR Priority PECI PEWFCSEI PERFCSEI PETEI 108 109 110 H 0001B0 H 0001B4 H 0001B8 ICRD2 High USB only in the H8S 2472 RESUME USBINT0 USBINT2 USBINT3 USB...

Page 139: ...ble 5 4 shows the interrupt control modes Table 5 4 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 ICR I Interrupt ma...

Page 140: ...priority 1 NMI and address break interrupts 1 0 All interrupts interrupt control level 1 has priority 1 0 NMI address break and interrupt control level 1 interrupts 1 NMI and address break interrupts...

Page 141: ...ith interrupt control level 1 priority and holds pending an interrupt request with interrupt control level 0 no priority If several interrupt requests are issued an interrupt request with the highest...

Page 142: ...ed by the contents of the vector address in the vector table Program execution state Interrupt generated NMI An interrupt with interrupt control level 1 IRQ0 IRQ1 EINT IRQ0 IRQ1 EINT I 0 Save PC and C...

Page 143: ...instance the state when the interrupt enable bit corresponding to each interrupt is set to 1 and ICRA to ICRD are set to H 20 H 00 H 00 and H 00 respectively IRQ2 and IRQ3 interrupts are set to interr...

Page 144: ...is cleared to 0 or when the I bit is set to 1 while the UI bit is cleared to 0 An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0 When both the I and UI bi...

Page 145: ...errupt with interrupt control level 1 IRQ0 IRQ1 EINT IRQ0 IRQ1 EINT UI 0 Save PC and CCR I 1 UI 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Ye...

Page 146: ...processing Interrupt is accepted Interrupt level decision and wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus 3 1...

Page 147: ...C CCR stack save 2 SK 4 Vector fetch 2 SI 5 Instruction fetch 3 2 SI 6 Internal processing 4 2 Total using on chip memory 12 to 32 Notes 1 Two states in case of internal interrupt 2 Refers to MULXS an...

Page 148: ...uest vector number Select signal Interrupt request Interrupt source clear signal IRQ interrupt On chip peripheral module Clear signal Interrupt controller I UI SWDTE clear signal Figure 5 8 Interrupt...

Page 149: ...r is performed first followed by CPU interrupt exception handling Table 5 9 summarizes interrupt source selection and interrupt source clearing control according to the settings of the DTCE bit of DTC...

Page 150: ...or that interrupt will be executed on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for th...

Page 151: ...PMOV B instruction and the EEPMOV W instruction With the EEPMOV B instruction an interrupt request including NMI issued during the transfer is not accepted until the move is completed With the EEPMOV...

Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...

Page 153: ...Possible in normal extended mode The external address space can be accessed as basic extended areas A 256 Kbyte extended area can be set and controlled independently of basic extended areas Address p...

Page 154: ...asic bus interface 2 state access or 3 state access can be selected for each area Program wait states can be inserted for each area Burst ROM interface In normal extended mode A burst ROM interface ca...

Page 155: ...rol register 2 Wait state control register Wait state control register 2 Internal control signals Internal data bus Wait controller BCR2 WSCR2 Bus mode signal Bus arbiter DTC bus acknowledge signal CP...

Page 156: ...space is being read HWR Output Strobe signal indicating that the external address space is being written to and the upper half D15 to D8 AD15 to AD8 of the data bus is valid LWR Output Strobe signal...

Page 157: ...used to specify the access mode for the external address space and the I O area range when the AS IOS pin is specified as an I O strobe pin Bit Bit Name Initial Value R W Description 7 1 R W Reserved...

Page 158: ...the burst cycle of the burst ROM interface 0 1 state 1 2 states 3 BRSTS0 0 R W Valid only in the normal extended mode Burst Cycle Select 0 Selects the number of words that can be accessed by burst acc...

Page 159: ...s Output Full Enable Controls the address output A23 to A21 in access to the extended area See section 8 I O Ports This is not supported while ADMXE 1 2 EXCKS 0 R W External Extension Clock Select Sel...

Page 160: ...hen the CS256E bit in SYSCR is set to 1 0 16 bit bus 1 8 bit bus 6 AST256 1 R W 256 Kbyte Extended Area Access State Control Selects the number of states for access to the 256 Kbyte extended area when...

Page 161: ...byte extended area 3 2 WMS1 WMS0 0 0 R W R W Basic Extended Area Wait Mode Select 1 and 0 Selects the wait mode for access to the basic extended area when the AST bit is set to 1 00 Program wait mode...

Page 162: ...the 256 Kbyte extended area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1 0 Program wait mode 1 Wait disabled mode 6 5 WC11 WC10 1 1 R W R W 256 Kbyte Extended Area Wait Count 1...

Page 163: ...for access to the address data multiplex extended area 0 Program wait state is not inserted 1 1 program wait state is inserted in the address cycle 1 0 All 1 R W Reserved 6 3 5 System Control Registe...

Page 164: ...bit setting c Wait Mode and Number of Program Wait States When the basic extended area is specified as a 3 state access space by the AST bit in WSCR the wait mode and the number of program wait states...

Page 165: ...s not selected while CS256E 1 CS256 is output and address pins A17 to A0 are used H FC0000 to H FEFFFF 192 Kbytes No condition H FF0800 to H FFBFFF 46 Kbytes When RAME 0 used as basic extended area H...

Page 166: ...0 Note In the burst ROM interface the bus width is specified by the ABW bit in WSCR the number of full access states wait can be inserted is specified by the AST bit in WSCR and the number of access c...

Page 167: ...ifications for 256 Kbyte Extended Area Basic Bus Interface Bus Specifications ABW256 AST256 WMS10 WC11 WC10 Bus Width Number of Access States Number of Program Wait States 0 X X X 16 2 0 1 X X 3 0 0 0...

Page 168: ...one program wait state can be inserted into address cycle From zero to three program wait states can be selected for data cycle 256 Kbyte Extended Area When the 256 Kbyte extended area is specified as...

Page 169: ...Kbytes No condition 256 Kbyte extended area H FA0000 to H FAFFFF 64 Kbytes No condition 256 Kbyte extended area H FB0000 to H FBFFFF 64 Kbytes No condition H FC0000 to H FFBFFF 240 Kbytes No conditio...

Page 170: ...S10 WC11 WC10 0 0 1 ABW256 AST256 WMS10 WC11 WC10 Table 6 8 Bus Specifications for IOS Extended Area Multiplex Bus Interface Address Cycle AST WMS1 WMS0 WC22 WC1 WC0 Number of Access States Number of...

Page 171: ...0 to H FFF7FF can be accessed by specifying the AS IOS pin as an I O strobe pin The 256 Kbyte extended area H F80000 to H FBFFFF can be accessed by the CS256 pin function The external address space is...

Page 172: ...2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR In the extended mode the IOS pin functions as an AS pin by a reset To use this pin as an IOS pi...

Page 173: ...pper data bus D15 to D8 AD15 to AD8 or lower data bus D7 to D0 AD7 to AD0 is used when the external address space is accessed according to the bus specifications for the area being accessed 8 bit acce...

Page 174: ...essed at one time is one byte or one word and a longword access is executed as two word accesses In byte access whether the upper or lower data bus is used is determined by whether the address is even...

Page 175: ...Read Write Address Valid Strobe Upper Data Bus D15 to D8 AD15 to AD8 Lower Data Bus D7 to D0 AD7 to AD0 Byte Read RD Valid Ports or others 8 bit access space Write HWR Byte Read RD Ports or others Va...

Page 176: ...4 Data Buses Used and Valid Strobes Gluless Extension Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower Data Bus D7 to D0 Byte Read RD Valid Ports or others 8 bit access...

Page 177: ...e When an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used Wait states cannot be inserted Bus cycle T1 T2 Address bus IOS IOSE 1 CS256 CS256E 1 AS IOSE 0 RD D15 to D8 Va...

Page 178: ...ce is accessed the upper half D15 to D8 of the data bus is used Wait states can be inserted Bus cycle T1 T2 Address bus AS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR D15 to D8 Valid Write T3...

Page 179: ...is used for even addresses and the lower half D7 to D0 for odd addresses Wait states cannot be inserted Bus cycle T1 T2 Address bus AS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8...

Page 180: ...RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 Undefined D7 to D0 Valid Write High level IOS IOSE 1 CS256 CS256E 1 Note For external address space access this signal is not output when the...

Page 181: ...AS IOSE 0 RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write IOS IOSE 1 CS256 CS256E 1 Note For external address space access this signal is not output when the 256 K...

Page 182: ...is used for even addresses and the lower half D7 to D0 for odd addresses Wait states can be inserted Bus cycle T1 T2 Address bus AS IOSE 0 RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Va...

Page 183: ...D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 Undefined D7 to D0 Valid Write High level T3 IOS IOSE 1 CS256 CS256E 1 Note For external address space access this signal is not output when th...

Page 184: ...S IOSE 0 RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write T3 IOS IOSE 1 CS256 CS256E 1 Note For external address space access this signal is not output when the 256...

Page 185: ...IOS IOSE 1 CS256 CS256E 1 Valid AS RD WR HBE LBE D15 to D8 Invalid D7 to D0 D15 to D8 D7 to D0 Even Valid Undefined For external address space access this signal is not output when the 256 Kbyte exten...

Page 186: ...IOS IOSE 1 CS256 CS256E 1 Invalid AS RD WR HBE LBE D15 to D8 Valid D7 to D0 D15 to D8 D7 to D0 Odd Undefined For external address space access this signal is not output when the 256 Kbyte extended ar...

Page 187: ...3 to A0 CS IOS IOSE 1 CS256 CS256E 1 valid AS RD WR HBE LBE D15 to D8 valid D7 to D0 D15 to D8 D7 to D0 Even Valid For external address space access this signal is not output when the 256 Kbyte extend...

Page 188: ...igures 6 16 and 6 17 show the bus timing for an 8 bit 2 state access space When an 8 bit access space is accessed the lower half AD7 to AD0 of the data bus is used Wait states cannot be inserted Read...

Page 189: ...2 State Access Space 2 8 Bit 3 State Data Access Space Figure 6 18 shows the bus timing for an 8 bit 3 state access space When an 8 bit access space is accessed the lower half AD7 to AD0 of the data b...

Page 190: ...space is accessed the upper half AD15 to AD8 of the data bus is used for even addresses and the lower half AD7 to AD0 for odd addresses Wait states cannot be inserted Read Cycle Address Data Data Writ...

Page 191: ...D15 to AD8 AD7 to AD0 Address Address Data Data Address Address Figure 6 20 Bus Timing for 16 Bit 2 State Access Space 2 Even Byte Access Read Cycle Address Data Data Write Cycle T1 T2 T3 TAW T4 Addre...

Page 192: ...1178 REJ09B0403 0100 Read Cycle Address Data Address Data Write Cycle T1 T2 T3 T4 T1 T2 T3 T4 CS256 IOS AH RD HWR LWR AD15 to AD8 AD7 to AD0 CK2S Address Address Data Data Address Address Figure 6 22...

Page 193: ...R AD15 to AD8 AD7 to AD0 Address Address Data Data Data Data Address Address Figure 6 23 Bus Timing for 16 Bit 2 State Access Space 5 Word Access Read Cycle Address Data Address Data Write Cycle T1 T2...

Page 194: ...is accessed the upper half AD15 to AD8 of the data bus is used for even addresses and the lower half AD7 to AD0 for odd addresses Wait states can be inserted Read Cycle Address Data Data Write Cycle T...

Page 195: ...AD7 to AD0 AD15 to AD8 Address Address Address Address Data Data Figure 6 26 Bus Timing for 16 Bit 3 State Access Space 2 Odd Byte Access Read Cycle Address Data Data Write Cycle T1 T2 T3 TAW T5 TDSW...

Page 196: ...of wait states TW is specified by the settings of the WC1 and WC0 bits If the WAIT pin is low at the falling edge of in the last T2 or TW state another TW state is inserted If the WAIT pin is held low...

Page 197: ...us Read data Read IOS IOSE 1 WR Write data Write Note shown in clock indicates the WAIT pin sampling timing WAIT Data bus T2 TW TW TW T3 By WAIT pin For external address space access this signal is no...

Page 198: ...ge of in the last T4 TDSW or TDOW state another TDOW state is inserted If the WAIT pin is held low TDOW states are inserted until it goes high Pin wait mode is useful when inserting four or more TDOW...

Page 199: ...2 2008 Page 151 of 1178 REJ09B0403 0100 Read Cycle Data Data Write Cycle T5 TDSW TDOW TDOW T3 T4 T5 TDSW TDOW TDOW T3 T4 CS256 IOS WAIT AH RD HWR LWR AD7 to AD0 Data Data AD15 to AD8 Data Data Figure...

Page 200: ...ace is determined by the AST bit in WSCR When the AST bit is set to 1 wait states can be inserted 1 or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR Wait...

Page 201: ...a Read data Read data AS IOS IOSE 0 Figure 6 31 Access Timing Example in Burst ROM Space AST BRSTS1 0 6 6 2 Wait Control As with the basic bus interface program wait insertion or pin wait insertion us...

Page 202: ...CR an idle cycle is inserted at the start of the write cycle Figure 6 32 shows examples of idle cycle operation In these examples bus cycle A is a read cycle for ROM with a long output floating time a...

Page 203: ...have bus mastership 6 8 2 Operation Each bus master requests the bus mastership by means of a bus mastership request signal The bus arbiter detects the bus mastership request signal from the bus maste...

Page 204: ...rring the bus mastership to the DTC 1 Bus mastership is transferred at a break between bus cycles However if bus cycle is executed in discrete operations as in the case of a longword size access the b...

Page 205: ...sferred at a break between bus cycles However if bus cycle is executed in discrete operations as in the case of a longword size access the bus is not transferred at a break between the operations In a...

Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...

Page 207: ...resses H FFEC00 to H FFEFFF in on chip RAM 1 kbyte enabling 32 bit 1 state reading and writing of the DTC register information 7 1 Features Transfer is possible over any number of channels Three trans...

Page 208: ...l data bus CPU interrupt request MRA MRB CRA CRB DAR SAR Interrupt request MRA MRB CRA CRB SAR DAR DTCERA to DTCERF DTVECR DTC mode register A B DTC transfer count register A B DTC source address regi...

Page 209: ...r count register B CRB These six registers cannot be directly accessed from the CPU When a DTC activation interrupt source occurs the DTC reads a set of register information that is stored in on chip...

Page 210: ...operation after a data transfer 0 DAR is fixed 10 DAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 11 DAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 3 2 MD1 MD0 Und...

Page 211: ...ndefined DTC Interrupt Select When this bit is set to 1 a CPU interrupt request is generated every time data transfer ends When this bit is cleared to 0 a CPU interrupt request is generated only when...

Page 212: ...block transfer mode It functions as a 16 bit transfer counter 1 to 65536 that is decremented by 1 every time data is transferred and transfer ends when the count reaches H 0000 7 2 7 DTC Enable Regist...

Page 213: ...The write value should always be 0 Only in the H8S 2472 7 2 8 DTC Vector Register DTVECR DTVECR enables or disables DTC activation by software and sets a vector number for the software activation inte...

Page 214: ...2 For example when DTVEC6 to DTVEC0 H 10 the vector address is H 0420 When the SWDTE bit is 0 these bits can be written to 7 2 9 Keyboard Comparator Control Register KBCOMP KBCOMP enables or disables...

Page 215: ...W Event Counter Channel Select 3 to 0 These bits select pins for event counter input A series of pins are selected starting from EVENT0 When PAnDDR is set to 1 inputting events to EVENT0 to EVENT7 is...

Page 216: ...to the state of this register Reading this register allows the monitoring of events that are not yet counted by the event counter Access in 8 bit unit is not allowed Bit Bit Name Initial Value R W Des...

Page 217: ...Identical optional RAM address Its lower five bits are B 00000 The start address of 16 words is this address They are incremented every time an event is detected in EVENT0 to EVENT15 CRAH 7 to 0 H FF...

Page 218: ...us Address Code ECS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Code 1 B 00000 1 0 B 00010 1 0 0 B 00100 1 0 0 0 B 00110 1 0 0 0 0 B 01000 1 0 0 0 0 0 B 01010 1 0 0 0 0 0 0 B 01100 1 0 0 0 0 0 0 0 B...

Page 219: ...tivated by an interrupt request or by a write to DTVECR by software The interrupt request source to activate the DTC is selected by DTCER At the end of a data transfer or the last consecutive transfer...

Page 220: ...78 REJ09B0403 0100 CPU DTC DTCER Source flag cleared On chip peripheral module IRQ interrupt Interrupt request Clear Clear controller Clear request Interrupt controller Selection circuit Interrupt mas...

Page 221: ...nformation start address should be located at the vector address corresponding to the interrupt source in the DTC vector table The DTC reads the start address of the register information from the vect...

Page 222: ...DTCEA4 A D converter ADI 28 H 0438 DTCEA3 EVC EVENTI 29 H 043A DTCEC4 IIC_2 IICI2 76 H 0498 DTCEB6 IIC_3 IICI3 78 H 049C DTCED4 SCI_3 RXI3 81 H 04A2 DTCEC2 TXI3 82 H 04A4 DTCEC1 SCI_1 RXI1 85 H 04AA D...

Page 223: ...fied as normal repeat or block transfer mode Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source chain transfer The 24 bit SAR designate...

Page 224: ...ansfers can be specified Once the specified number of transfers has been completed a CPU interrupt can be requested Table 7 5 Register Functions in Normal Mode Name Abbreviation Function DTC source ad...

Page 225: ...epeat area is restored and transfer is repeated In repeat mode the transfer counter value does not reach H 00 and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0...

Page 226: ...restored The other address register is then incremented decremented or left fixed according to the register information From 1 to 65 536 transfers can be specified Once the specified number of transfe...

Page 227: ...ster information at that start address After the data transfer the CHNE bit will be tested When it has been set to 1 DTC reads the next register information located in a consecutive area and performs...

Page 228: ...are activated data transfer end interrupt SWDTEND is generated When the DISEL bit is 1 and one data transfer has been completed or the specified number of transfers have been completed after data tran...

Page 229: ...Transfer information write Data transfer Figure 7 10 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 DTC activation request DTC request Address Vector read Read Write Read Wri...

Page 230: ...fer 1 6 N N 3 Legend N Block size initial setting of CRAH and CRAL Table 7 9 Number of States Required for Each Execution Status Object to be Accessed On Chip RAM H FFEC00 to H FFEFFF On Chip RAM On c...

Page 231: ...Set the enable bits for the interrupt sources to be used as the activation sources to 1 The DTC is activated when an interrupt used as an activation source is generated 5 After one data transfer has...

Page 232: ...ress 3 Set the corresponding bit in DTCER to 1 4 Set the SCI to the appropriate receive mode Set the RIE bit in SCR to 1 to enable the reception complete RXI interrupt Since the generation of a receiv...

Page 233: ...destination address H 2000 in DAR and 128 H 8080 in CRA Set 1 H 0001 in CRB 2 Set the start address of the register information at the DTC vector address H 04C0 3 Check that the SWDTE bit in DTVECR is...

Page 234: ...MRB SAR DAR CRA and CRB are all located in on chip RAM When the DTC is used the RAME bit in SYSCR should not be cleared to 0 7 9 3 DTCE Bit Setting For DTCE bit setting use bit manipulation instructio...

Page 235: ...and D0 to D5 pins the on off status of the input pull up MOS is controlled by their respective DDR and the output data register ODR Ports 1 to 3 and 6 have an input pull up MOS control register PCR in...

Page 236: ...P20 A8 AD8 Port 3 General I O port multiplexed with de bounced input and bidirectional data bus I O P37 ExDB7 P36 ExDB6 P35 ExDB5 P34 ExDB4 P33 ExDB3 P32 ExDB2 P31 ExDB1 P30 ExDB0 P37 ExDB7 D15 P36 E...

Page 237: ...67 ExIRQ8 SSCK P66 ExIRQ9 SCS P65 ExIRQ10 RTS P64 ExIRQ11 CTS Same as left Built in input pull up MOS General I O port multiplexed with interrupt input PWMX output and bidirectional data bus I O P63 P...

Page 238: ...ExIRQ7 EVENT7 A23 PA6 ExIRQ6 EVENT6 A22 LNKSTA PA5 ExIRQ5 EVENT5 A21 WOL PA4 ExIRQ4 EVENT4 A20 PA3 ExIRQ3 EVENT3 A19 PA2 ExIRQ2 EVENT2 A18 PA1 ExIRQ1 EVENT1 A17 PA0 ExIRQ0 EVENT0 A16 Built in input p...

Page 239: ...lexed with LPC I O PD5 LPCPD PD4 CLKRUN PD3 GA20 PD2 PME PD1 LSMI PD0 LSCI Same as left Built in input pull up MOS Port E General I O port multiplexed with LPC I O PE7 SERIRQ PE6 LCLK PE5 LRESET PE4 L...

Page 240: ...r P1DDR The individual bits of P1DDR specify input or output for the pins of port 1 Bit Bit Name Initial Value R W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR...

Page 241: ...values are read for the bits with the corresponding P1DDR bits set to 1 For the bits with the corresponding P1DDR bits cleared to 0 the pin states are read 3 Port 1 Pull Up MOS Control Register P1PCR...

Page 242: ...ut pin An output pin Setting prohibited P1n output pin Legend n 7 to 0 X Don t care b Single Chip Mode EXPE 0 The pin function is switched as shown below according to the P1nDDR bit P1nDDR 0 1 Pin fun...

Page 243: ...Name Initial Value R W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W When set to 1 the corresponding pins function as output port pins when cleared to 0 function as input port pins 3...

Page 244: ...bits set to 1 For the bits with the corresponding P2DDR bits cleared to 0 the pin states are read 3 Port 2 Pull Up MOS Control Register P2PCR P2PCR controls the port 2 built in input pull up MOSs Bit...

Page 245: ...the combination of the CS256E and IOSE bits in SYSCR the ADFULLE bit in BCR2 of the BSC and the P23DDR bit Address 11 in the table below is expressed by the following logical expression Address 11 1...

Page 246: ...CIFOE0 Other than 10 10 X1 X0 P27DDR 0 1 X 0 1 X Pin function P27 input pin P27 output pin DTR output pin P27 input pin P27 output pin DTR output pin Legend X Don t care P26 DSR P25 RI P24 DCD The pin...

Page 247: ...be controlled by software The input pull up MOS can be used regardless of the operating mode Table 8 3 summarizes the input pull up MOS states Table 8 3 Port 2 Input Pull Up MOS States Reset Hardware...

Page 248: ...r P3PCR Noise canceler enable register P3NCE Noise canceler mode control register P3NCMC Noise cancel cycle setting register NCCS 1 Port 3 Data Direction Register P3DDR The individual bits of P3DDR sp...

Page 249: ...ding P3DDR bits cleared to 0 1 is read Other modes P3DR stores output data for the port 3 pins that are used as the general output port If this register is read the P3DR values are read for the bits w...

Page 250: ...ing pin and the pin state is fetched into P3DR at the sampling cycle set by NCCS The operation changes according to the other control bits 5 Noise Canceler Mode Control Register P3NCMC When the noise...

Page 251: ...alue is read from these bits 2 1 0 NCCK2 NCCK1 NCCK0 0 0 0 R W R W R W These bits set the sampling cycle of the noise cancelers When 34 MHz 000 0 06 s 2 100 963 8 s 32768 001 0 94 s 32 101 1 9 ms 6553...

Page 252: ...rt 3 pins are automatically set to function as bidirectional data bus pins b Address Data Multiplex Extended Mode The operation is the same as that in single chip mode c Single Chip Mode The pin funct...

Page 253: ...d address data multiplex extended mode Table 8 4 summarizes the input pull up MOS states Table 8 4 Port 3 Input Pull Up MOS States Mode Reset Hardware Standby Mode Software Standby Mode In Other Opera...

Page 254: ...dual bits of P4DDR specify input or output for the port 4 pins P4DDR is initialized only by a system reset and retains the value even if an internal reset signal of the WDT is generated Bit Bit Name I...

Page 255: ...tput data for the port 4 pins that are used as the general output port If this register is read the P4DR values are read for the bits with the corresponding P4DDR bits set to 1 For the bits with the c...

Page 256: ...r modes When the pins are in the input state the corresponding input pull up MOS is turned on when a P4PCR bit is set to 1 4 Noise Canceler Enable Register P4BNCE The individual bits of P4BNCE enable...

Page 257: ...nput stably 0 expected 0 is stored in the port data register while 0 is input stably 3 to 0 PB3NCMC to PB0NCMC All 1 R W Bits for port B setting 6 Noise Canceler Cycle Setting Register NCCS NCCS contr...

Page 258: ...atch Pin input Sampling clock selection Sampling clock Match detection circuit Port data register Latch Latch 2 32 512 8192 32768 65536 131072 262144 t Figure 8 3 Noise Canceler Circuit P4n input 1 ex...

Page 259: ...DR bit Address 13 in the table below is expressed by the following logical expression Address 13 1 ADFULLE CS256E IOSE P4nDDR 0 1 Address 13 X 0 1 Pin function P4n input pin Am output pin P4n output p...

Page 260: ...e used as the IRQn input pin To use as the IRQn input pin clear the P4nDDR bit to 0 P4nDDR 0 1 P4nNCE 0 1 X P4n input DBn input Pin function IRQn input IRQn input with the noise canceler P4n output Le...

Page 261: ...d address data multiplex extended mode Table 8 5 summarizes the input pull up MOS states Table 8 5 Port 4 Input Pull Up MOS States Mode Reset Hardware Standby Mode Software Standby Mode In Other Opera...

Page 262: ...for the port 5 pins Bit Bit Name Initial Value R W Description 7 P57DDR 0 W If port 5 pins are specified for use as the general I O port the corresponding pins function as output port when the P5DDR b...

Page 263: ...h the corresponding P5DDR bits cleared to 0 the pin states are read Note The initial value is determined in accordance with the pin state of P56 3 Pin Functions a Normal Extended Mode and Address Data...

Page 264: ...the interrupt controller is set to 1 this pin can be used as the IRQ13 input pin To use as the IRQ13 input pin clear the P55DDR bit to 0 RE 0 1 P55DDR 0 1 X P55 input pin Pin function IRQ13 input pin...

Page 265: ...ear the P53DDR bit to 0 RE 0 1 P53DDR 0 1 X P53 input pin Pin function IRQ11 input pin P53 output pin RxD1 input pin Legend X Don t care P52 IRQ10 TxD1 The pin function is switched as shown below acco...

Page 266: ...bit to 0 SCIF Disabled Enabled P51DDR 0 1 X P51 input pin Pin function IRQ9 input pin P51 output pin RxDF input pin Legend X Don t care P50 IRQ8 TxDF The pin function is switched as shown below accor...

Page 267: ...ister P6PCR 1 Port 6 Data Direction Register P6DDR The individual bits of P6DDR specify input or output for the pins of port 6 Bit Bit Name Initial Value R W Description 7 P67DDR 0 W 6 P66DDR 0 W 5 P6...

Page 268: ...e pin states are read 3 P63DR 0 R W 2 P62DR 0 R W 1 P61DR 0 R W 0 P60DR 0 R W Normal extended mode 16 bit data bus Since the corresponding pins function as bidirectional data bus pins the value in the...

Page 269: ...e pins are in the input state the corresponding input pull up MOS is turned on when a P6PCR bit is set to 1 4 Pin Functions a Normal Extended Mode 16 bit bus mode Port pins 63 to 60 are automatically...

Page 270: ...CSS0 bits in SSCRH of the SSU and the P66DDR bit When the ISS9 bit in ISSR16 is set to 1 this pin can be used as the ExIRQ9 input pin To use as the ExIRQ9 input pin clear the P66DDR bit to 0 CSS1 CSS0...

Page 271: ...IRQ11 input pin P64 output pin CTS input pin Legend X Don t care P63 PWX3 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of...

Page 272: ...shown below according to the combination of the OEA bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P60DDR bit To use this pin as the IRQ14 input pin clear the P60DDR bit to 0 P60DDR 0 1 X P...

Page 273: ...R 1 P71PIN Undefined R 0 P70PIN Undefined R When this register is read the pin states are read Since this register is allocated to the same address as PBDDR writing to this register writes data to PBD...

Page 274: ...ccording to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A D converter Do not set these bits to other values than those shown in the following table SCANE 0 1 CH2 t...

Page 275: ...CR and the CH2 to CH0 bits in ADCSR of the A D converter Do not set these bits to other values than those shown in the following table SCANE 0 1 SCANS X 0 1 CH2 to CH0 B 010 Other than B 010 B 010 to...

Page 276: ...nd SCANS bits in ADCR and the CH2 to CH0 bits in ADCSR of the A D converter Do not set these bits to other values than those shown in the following table SCANE 0 1 SCANS X 0 1 CH2 to CH0 B 000 Other t...

Page 277: ...P8DDR Port 8 data register P8DR 1 Port 8 Data Direction Register P8DDR The individual bits of P8DDR specify input or output for the port 8 pins Bit Bit Name Initial Value R W Description 7 P87DDR 0 W...

Page 278: ...0 the pin states are read 3 Pin Functions The relationship between register setting values and pin functions are as follows P87 ExIRQ15 TxD3 ADTRG The pin function is switched as shown below according...

Page 279: ...0 RE 0 1 0 P86 input pin Pin function ExIRQ14 input pin RxD3 input pin RxD3 input output pin P86 output pin P85 ExIRQ13 SCK1 The pin function is switched as shown below according to the combination of...

Page 280: ...t to 0 CKE1 0 1 C A 0 1 X CKE0 0 1 X X P84DDR 0 1 X X X P84 input pin Pin function ExIRQ12 input pin P84 output pin SCK3 output pin SCK3 output pin SCK3 input pin Legend X Don t care P83 SDA1 The pin...

Page 281: ...he combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit When this pin is used as the P81 output pin the output format is NMOS push pull output The output format for SDA0 is NMOS open drain o...

Page 282: ...ection register P9DDR Port 9 data register P9DR 1 Port 9 Data Direction Register P9DDR The individual bits of P9DDR specify input or output for the port 9 pins Bit Bit Name Initial Value R W Descripti...

Page 283: ...e corresponding P9DDR bits set to 1 For the bits with the corresponding P9DDR bits cleared to 0 the pin states are read 3 Pin Functions The relationship between register setting values and pin functio...

Page 284: ...output pin P95 input pin P95 output pin Legend X Don t care P94 ExPWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of t...

Page 285: ...unction is switched as shown below according to the operating mode the ADMXE bit in SYSCR2 and the P91DDR bit Operating mode Extended mode Single chip mode ADMXE 0 1 X P91DDR 0 1 X 0 1 Pin function P9...

Page 286: ...ort A output data register PAODR Port A input data register PAPIN 1 Port A Data Direction Register PADDR The individual bits of PADDR specify input or output for the port A pins Bit Bit Name Initial V...

Page 287: ...eneral output port 3 Port A Input Data Register PAPIN PAPIN indicates the states of the port A pins Bit Bit Name Initial Value R W Description 7 PA7PIN Undefined R 6 PA6PIN Undefined R 5 PA5PIN Undefi...

Page 288: ...module Address 18 1 ADFULLE Address 13 1 ADFULLE CS256E IOSE PA7 ExIRQ7 EVENT7 A23 EXOUT The pin function is switched as shown below according to the setting of address 18 and the PA7DDR bit Setting...

Page 289: ...e LNKSTA input pin PA6DDR 0 1 1 Address 18 1 0 PA6 input pin Pin function ExIRQ6 input pin EVENT6 input pin PA6 output pin A22 output pin PA5 ExIRQ5 EVENT5 A21 WOL The pin function is switched as show...

Page 290: ...1 1 Address 18 X 1 0 PAn input pin Pin function ExIRQn input pin EVENTn input pin PAn output pin Am output pin Legend n 4 to 2 m 20 to 18 X Don t care PA1 ExIRQ1 EVENT1 A17 PA0 ExIRQ0 EVENT0 A16 The...

Page 291: ...ut pin When the module stop mode is cleared in both the EtherC and E DMAC this pin functions as the EXOUT output pin PA7DDR 0 1 PA7 input pin Pin function ExIRQ7 input pin EVENT7 input pin PA7 output...

Page 292: ...h the EtherC and E DMAC this pin functions as the WOL input pin PA5DDR 0 1 PA5 input pin Pin function ExIRQ5 input pin EVENT5 input pin PA5 output pin PA4 ExIRQ4 EVENT4 PA3 ExIRQ3 EVENT3 PA2 ExIRQ2 EV...

Page 293: ...t basis PAnDDR 0 1 PAnODR 1 0 X PAn pull up MOS ON OFF OFF Legend n 7 to 0 X Don t care The input pull up MOS is in the off state after a reset and in hardware standby mode The prior state is retained...

Page 294: ...output data register PBODR Port B input data register PBPIN Noise canceler enable register P4BNCE Noise canceler mode control register P4BNCMC Noise cancel cycle setting register NCCS 1 Port B Data Di...

Page 295: ...output port 3 Port B Input Data Register PBPIN PBPIN indicates the states of the port B pins Bit Bit Name Initial Value R W Description 7 PB7PIN Undefined R 6 PB6PIN Undefined R 5 PB5PIN Undefined R 4...

Page 296: ...te is fetched into PBDR at the sampling cycle set by NCCS The operation changes according to the other control bits See section 8 1 11 7 Pin Functions for details 5 Noise Canceler Mode Control Registe...

Page 297: ...alue is read from these bits 2 1 0 NCCK2 NCCK1 NCCK0 0 0 0 R W R W R W These bits set the sampling cycle of the noise cancelers When 34 MHz 000 0 06 s 2 100 963 8 s 32768 001 0 94 s 32 101 1 9 ms 6553...

Page 298: ...Section 8 I O Ports Rev 1 00 Mar 12 2008 Page 250 of 1178 REJ09B0403 0100 PBn input 1 expected PBnDR 0 expected PBnDR n 3 to 0 Figure 8 6 Noise Canceler Operation...

Page 299: ...X X Pin function PBn input pin EVENTm input pin PBn output pin RM_xxxx EtherC I O pin Legend n 7 to 4 m 15 to 12 X Don t care Note See section 7 3 DTC Event Counter for the event counter settings PB3...

Page 300: ...utput data register PCODR Port C input data register PCPIN 1 Port C Data Direction Register PCDDR The individual bits of PCDDR specify input or output for the port C pins Bit Bit Name Initial Value R...

Page 301: ...general output port 3 Port C Input Data Register PCPIN PCPIN indicates the pin states of port C Bit Bit Name Initial Value R W Description 7 PC7PIN Undefined R 6 PC6 PIN Undefined R 5 PC5PIN Undefined...

Page 302: ...us width the PC7 pin functions as a bus control output pin When 8 bit bus width the pin function is the same as that in single chip mode PC5 to PC0 The pin functions are the same as those in single ch...

Page 303: ...of the IIC_3 and the PC3DDR bit ICE 0 1 PC3DDR 0 1 X Pin function PC3 input pin PC3 output pin SDA3 input output pin Legend X Don t care PC2 SCL3 The pin function is switched as shown below according...

Page 304: ...REJ09B0403 0100 PC0 SCL2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC0DDR bit ICE 0 1 PC0DDR 0 1 X Pin function PC0 input pin...

Page 305: ...register PDPIN 1 Port D Data Direction Register PDDDR The individual bits of PDDDR specify input or output for the port D pins Bit Bit Name Initial Value R W Description 7 PD7DDR 0 W 6 PD6DDR 0 W 5 P...

Page 306: ...general output port 3 Port D Input Data Register PDPIN PDPIN indicates the pin states of port D Bit Bit Name Initial Value R W Description 7 PD7PIN Undefined R 6 PD6 PIN Undefined R 5 PD5PIN Undefined...

Page 307: ...of the ICE bit in ICCR of the IIC_5 and the PD7DDR bit ICE 0 1 PD7DDR 0 1 X Pin function PD7 input pin PD7 output pin SDA5 input output pin Legend X Don t care PD6 SCL5 The pin function is switched as...

Page 308: ...o the combination of the FGA20E bit in HICR0 of the LPC and the PD3DDR bit FGA20E 0 1 PD3DDR 0 1 0 Pin function PD3 input pin PD3 output pin GA20 output pin PD2 PME The pin function is switched as sho...

Page 309: ...ftware This input pull up MOS can be used in any operating mode and can be specified as on or off on a bit by bit basis PDnDDR 0 1 PDnODR 1 0 X PDn pull up MOS ON OFF OFF Legend n 5 to 0 X Don t care...

Page 310: ...R 0 W 6 PE6DDR 0 W 5 PE5DDR 0 W 4 PE4DDR 0 W 3 PE3DDR 0 W 2 PE2DDR 0 W 1 PE1DDR 0 W 0 PE0DDR 0 W When set to 1 the corresponding pins function as output port pins when cleared to 0 function as input p...

Page 311: ...o this register writes data to PEDDR and the port E setting is changed Note The initial value of these pins is determined in accordance with the state of pins PE7 to PE0 4 Pin Functions Port E pins ca...

Page 312: ...d and the PE5DDR bit LPC Disabled Enabled PE5DDR 0 1 X Pin function PE5 input pin PE5 output pin LRESET input pin Legend X Don t care PE4 LFRAME The pin function is switched as shown below according t...

Page 313: ...nd X Don t care PE1 LAD1 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE1DDR bit LPC Disabled Enabled PE1DDR 0 1 X Pin function PE1 input pin...

Page 314: ...individual bits of PFDDR specify input or output for the port F pins PFDDR is initialized only by a system reset and retains the value even if an internal reset signal of the WDT is generated Bit Bit...

Page 315: ...res the output data for the pin that is used as the general output port 3 Port F Input Data Register PFPIN PFPIN indicates the pin states of port F Bit Bit Name Initial Value R W Description 7 Reserve...

Page 316: ...WMXS 0 1 0 1 1 OEA X 0 X 0 1 Pin function PF6 input pin PF6 output pin ExPWX2 output pin Legend X Don t care PF5 RS13 The pin function is switched as shown below according to the PF5DDR bit PF5DDR 0 1...

Page 317: ...PF2 input pin PF2 output pin PF1 RS9 MDC PF0 RS8 MDIO The pin function is switched as shown below according to the combination of the module stop state in the EtherC and E DMAC and the PFnDDR bit Eth...

Page 318: ...D5 pins the on off status of the input pull up MOS is controlled by their respective DDR and the output data register ODR Ports 1 to 3 and 6 have an input pull up MOS control register PCR in addition...

Page 319: ...P20 A8 AD8 Port 3 General I O port multiplexed with de bounced input and bidirectional data bus I O P37 ExDB7 P36 ExDB6 P35 ExDB5 P34 ExDB4 P33 ExDB3 P32 ExDB2 P31 ExDB1 P30 ExDB0 P37 ExDB7 D15 P36 E...

Page 320: ...67 ExIRQ8 SSCK P66 ExIRQ9 SCS P65 ExIRQ10 RTS P64 ExIRQ11 CTS Same as left Built in input pull up MOS General I O port multiplexed with interrupt input PWMX output and bidirectional data bus I O P63 P...

Page 321: ...IRQ7 EVENT7 A23 PA6 ExIRQ6 EVENT6 LNKSTA A22 PA5 ExIRQ5 EVENT5 WOL A21 PA4 ExIRQ4 EVENT4 A20 PA3 ExIRQ3 EVENT3 A19 PA2 ExIRQ2 EVENT2 A18 PA1 ExIRQ1 EVENT1 A17 PA0 ExIRQ0 EVENT0 A16 Built in input pull...

Page 322: ...neral I O port multiplexed with LPC I O PD5 LPCPD PD4 CLKRUN PD3 GA20 PD2 PME PD1 LSMI PD0 LSCI Same as left Built in input pull up MOS Port E General I O port multiplexed with LPC I O PE7 SERIRQ PE6...

Page 323: ...r P1DDR The individual bits of P1DDR specify input or output for the pins of port 1 Bit Bit Name Initial Value R W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR...

Page 324: ...values are read for the bits with the corresponding P1DDR bits set to 1 For the bits with the corresponding P1DDR bits cleared to 0 the pin states are read 3 Port 1 Pull Up MOS Control Register P1PCR...

Page 325: ...t pin An output pin Setting prohibited P1n output pin Legend n 7 to 0 X Don t care b Single Chip Mode EXPE 0 The pin function is switched as shown below according to the P1nDDR bit P1nDDR 0 1 Pin func...

Page 326: ...Name Initial Value R W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W When set to 1 the corresponding pins function as output port pins when cleared to 0 function as input port pins 3...

Page 327: ...bits set to 1 For the bits with the corresponding P2DDR bits cleared to 0 the pin states are read 3 Port 2 Pull Up MOS Control Register P2PCR P2PCR controls the port 2 built in input pull up MOSs Bit...

Page 328: ...the combination of the CS256E and IOSE bits in SYSCR the ADFULLE bit in BCR2 of the BSC and the P23DDR bit Address 11 in the table below is expressed by the following logical expression Address 11 1...

Page 329: ...CIFOE0 Other than 10 10 X1 X0 P27DDR 0 1 X 0 1 X Pin function P27 input pin P27 output pin DTR output pin P27 input pin P27 output pin DTR output pin Legend X Don t care P26 DSR P25 RI P24 DCD The pin...

Page 330: ...be controlled by software The input pull up MOS can be used regardless of the operating mode Table 8 11 summarizes the input pull up MOS states Table 8 11 Port 2 Input Pull Up MOS States Reset Hardwar...

Page 331: ...r P3PCR Noise canceler enable register P3NCE Noise canceler mode control register P3NCMC Noise cancel cycle setting register NCCS 1 Port 3 Data Direction Register P3DDR The individual bits of P3DDR sp...

Page 332: ...ding P3DDR bits cleared to 0 1 is read Other modes P3DR stores output data for the port 3 pins that are used as the general output port If this register is read the P3DR values are read for the bits w...

Page 333: ...te is fetched into P3DR at the sampling cycle set by NCCS The operation changes according to the other control bits See section 8 2 3 7 Pin Functions for details 5 Noise Canceler Mode Control Register...

Page 334: ...alue is read from these bits 2 1 0 NCCK2 NCCK1 NCCK0 0 0 0 R W R W R W These bits set the sampling cycle of the noise cancelers When 34 MHz 000 0 06 s 2 100 963 8 s 32768 001 0 94 s 32 101 1 9 ms 6553...

Page 335: ...ded Mode Port 3 pins are automatically set to function as bidirectional data bus pins b Address Data Multiplex Extended Mode The operation is the same as that in single chip mode c Single Chip Mode Th...

Page 336: ...address data multiplex extended mode Table 8 12 summarizes the input pull up MOS states Table 8 12 Port 3 Input Pull Up MOS States Mode Reset Hardware Standby Mode Software Standby Mode In Other Oper...

Page 337: ...dual bits of P4DDR specify input or output for the port 4 pins P4DDR is initialized only by a system reset and retains the value even if an internal reset signal of the WDT is generated Bit Bit Name I...

Page 338: ...tput data for the port 4 pins that are used as the general output port If this register is read the P4DR values are read for the bits with the corresponding P4DDR bits set to 1 For the bits with the c...

Page 339: ...re in the input state the corresponding input pull up MOS is turned on when a P4PCR bit is set to 1 4 Noise Canceler Enable Register P4BNCE The individual bits of P4BNCE enable or disable the noise ca...

Page 340: ...nput stably 0 expected 0 is stored in the port data register while 0 is input stably 3 to 0 PB3NCMC to PB0NCMC All 1 R W Bits for port B setting 6 Noise Canceler Cycle Setting Register NCCS NCCS contr...

Page 341: ...atch Pin input Sampling clock selection Sampling clock Match detection circuit Port data register Latch Latch 2 32 512 8192 32768 65536 131072 262144 t Figure 8 9 Noise Canceler Circuit P4n input 1 ex...

Page 342: ...bit Address 13 in the table below is expressed by the following logical expression Address 13 1 ADFULLE CS256E IOSE P4nDDR 0 1 Address 13 X 0 1 Pin function P4n input pin Am output pin P4n output pin...

Page 343: ...he IRQn input pin To use as the IRQn input pin clear the P4nDDR bit to 0 P4nDDR 0 1 P4nNCE 0 1 X P4n input DBn input Pin function IRQn input IRQn input with the noise canceler P4n output pin Legend n...

Page 344: ...address data multiplex extended mode Table 8 13 summarizes the input pull up MOS states Table 8 13 Port 4 Input Pull Up MOS States Mode Reset Hardware Standby Mode Software Standby Mode In Other Oper...

Page 345: ...for the port 5 pins Bit Bit Name Initial Value R W Description 7 P57DDR 0 W If port 5 pins are specified for use as the general I O port the corresponding pins function as output port when the P5DDR b...

Page 346: ...h the corresponding P5DDR bits cleared to 0 the pin states are read Note The initial value is determined in accordance with the pin state of P56 3 Pin Functions a Normal Extended Mode and Address Data...

Page 347: ...the interrupt controller is set to 1 this pin can be used as the IRQ13 input pin To use as the IRQ13 input pin clear the P55DDR bit to 0 RE 0 1 P55DDR 0 1 X P55 input pin Pin function IRQ13 input pin...

Page 348: ...ear the P53DDR bit to 0 RE 0 1 P53DDR 0 1 X P53 input pin Pin function IRQ11 input pin P53 output pin RxD1 input pin Legend X Don t care P52 IRQ10 TxD1 The pin function is switched as shown below acco...

Page 349: ...bit to 0 SCIF Disabled Enabled P51DDR 0 1 X P51 input pin Pin function IRQ9 input pin P51 output pin RxDF input pin Legend X Don t care P50 IRQ8 TxDF The pin function is switched as shown below accor...

Page 350: ...ister P6PCR 1 Port 6 Data Direction Register P6DDR The individual bits of P6DDR specify input or output for the pins of port 6 Bit Bit Name Initial Value R W Description 7 P67DDR 0 W 6 P66DDR 0 W 5 P6...

Page 351: ...e pin states are read 3 P63DR 0 R W 2 P62DR 0 R W 1 P61DR 0 R W 0 P60DR 0 R W Normal extended mode 16 bit data bus Since the corresponding pins function as bidirectional data bus pins the value in the...

Page 352: ...W 0 P60PCR 0 R W Normal extended mode 16 bit bus This register has no effect on operation Other modes When the pins are in the input state the corresponding input pull up MOS is turned on when a P6PCR...

Page 353: ...ISSR16 is set to 1 this pin can be used as the ExIRQ8 input pin To use as the ExIRQ8 input pin clear the P67DDR bit to 0 SCKS 0 1 P67DDR 0 1 X P67 input pin Pin function ExIRQ8 input pin P67 output p...

Page 354: ...ExIRQ11 CTS The pin function is switched as shown below according to the combination of the enable disable setting of the SCIF and the P64DDR bit When the ISS10 bit in ISSR16 is set to 1 this pin can...

Page 355: ...the OEB bit in DACR and the PWMXS bit in PTCNT0 of PWMX_0 and the P61DDR bit To use this pin as the IRQ15 input pin clear the P61DDR bit to 0 P61DDR 0 1 X PWMXS 0 1 0 1 0 OEB 0 X 0 X 1 P61 input pin P...

Page 356: ...nput pull up MOSs that can be controlled by software Table 8 14 summarizes the input pull up MOS states Table 8 14 Port 6 Input Pull Up MOS States Reset Hardware Standby Mode Software Standby Mode In...

Page 357: ...es of the port 7 pins Bit Bit Name Initial Value R W Description 7 P77PIN Undefined R 6 P76PIN Undefined R 5 P75PIN Undefined R 4 P74PIN Undefined R 3 P73PIN Undefined R 2 P72PIN Undefined R 1 P71PIN...

Page 358: ...ording to the combination of the SCANE bit in ADCR and the CH2 to CH0 bits in ADCSR of the A D converter Do not set these bits to other values than those shown in the following table SCANE 0 1 CH2 to...

Page 359: ...A D converter Do not set these bits to other values than those shown in the following table SCANE 0 1 SCANS X 0 1 CH2 to CH0 B 011 Other than B 011 B 011 Other than B 011 B 011 to B 111 B 000 to B 01...

Page 360: ...to B 011 B 001 to B 111 B 000 Pin function AN1 input pin P71 input pin AN1 input pin P71 input pin AN1 input pin P71 input pin Legend X Don t care P70 AN0 The pin function is switched as shown below a...

Page 361: ...P8DDR Port 8 data register P8DR 1 Port 8 Data Direction Register P8DDR The individual bits of P8DDR specify input or output for the port 8 pins Bit Bit Name Initial Value R W Description 7 P87DDR 0 W...

Page 362: ...0 the pin states are read 3 Pin Functions The relationship between register setting values and pin functions are as follows P87 ExIRQ15 TxD3 ADTRG The pin function is switched as shown below according...

Page 363: ...0 RE 0 1 0 P86 input pin Pin function ExIRQ14 input pin RxD3 input pin RxD3 input output pin P86 output pin P85 ExIRQ13 SCK1 The pin function is switched as shown below according to the combination of...

Page 364: ...t to 0 CKE1 0 1 C A 0 1 X CKE0 0 1 X X P84DDR 0 1 X X X P84 input pin Pin function ExIRQ12 input pin P84 output pin SCK3 output pin SCK3 output pin SCK3 input pin Legend X Don t care P83 SDA1 The pin...

Page 365: ...he combination of the ICE bit in ICCR of IIC_0 and the P81DDR bit When this pin is used as the P81 output pin the output format is NMOS push pull output The output format for SDA0 is NMOS open drain o...

Page 366: ...ection register P9DDR Port 9 data register P9DR 1 Port 9 Data Direction Register P9DDR The individual bits of P9DDR specify input or output for the port 9 pins Bit Bit Name Initial Value R W Descripti...

Page 367: ...e corresponding P9DDR bits set to 1 For the bits with the corresponding P9DDR bits cleared to 0 the pin states are read 3 Pin Functions The relationship between register setting values and pin functio...

Page 368: ...output pin P95 input pin P95 output pin Legend X Don t care P94 ExPWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR and the PWMXS bit in PTCNT0 of t...

Page 369: ...unction is switched as shown below according to the operating mode the ADMXE bit in SYSCR2 and the P91DDR bit Operating mode Extended mode Single chip mode ADMXE 0 1 X P91DDR 0 1 X 0 1 Pin function P9...

Page 370: ...DDR Port A output data register PAODR Port A input data register PAPIN 1 Port A Data Direction Register PADDR The individual bits of PADDR specify input or output for the port A pins Bit Bit Name Init...

Page 371: ...eneral output port 3 Port A Input Data Register PAPIN PAPIN indicates the states of the port A pins Bit Bit Name Initial Value R W Description 7 PA7PIN Undefined R 6 PA6PIN Undefined R 5 PA5PIN Undefi...

Page 372: ...other module Address 18 1 ADFULLE Address 13 1 ADFULLE CS256E IOSE PA7 ExIRQ7 EVENT7 A23 EXOUT The pin function is switched as shown below according to the setting of address 18 and the PA7DDR bit Set...

Page 373: ...e LNKSTA input pin PA6DDR 0 1 1 Address 18 1 0 PA6 input pin Pin function ExIRQ6 input pin EVENT6 input pin PA6 output pin A22 output pin PA5 ExIRQ5 EVENT5 A21 WOL The pin function is switched as show...

Page 374: ...PAn input pin Pin function ExIRQn input pin EVENTn input pin PAn output pin Am output pin Legend n 4 to 2 m 20 to 18 X Don t care PA1 ExIRQ1 EVENT1 A17 PA0 ExIRQ0 EVENT0 A16 The pin function is switch...

Page 375: ...as the PA7 output pin When the module stop mode is cleared in both the EtherC and E DMAC this pin functions as the EXOUT output pin PA7DDR 0 1 PA7 input pin Pin function ExIRQ7 input pin EVENT7 input...

Page 376: ...n PA5 output pin PA4 ExIRQ4 EVENT4 PA3 ExIRQ3 EVENT3 PA2 ExIRQ2 EVENT2 PA1 ExIRQ1 EVENT1 PA0 ExIRQ0 EVENT0 The pin function is switched as shown below according to the PAnDDR bit Setting the ISSn bit...

Page 377: ...nd in hardware standby mode The prior state is retained in software standby mode Table 8 15 summarizes the input pull up MOS states Table 8 15 Input Pull Up MOS States Reset Hardware Standby Mode Soft...

Page 378: ...B output data register PBODR Port B input data register PBPIN Noise canceler enable register P4BNCE Noise canceler mode control register P4BNCMC Noise cancel cycle setting register NCCS 1 Port B Data...

Page 379: ...output port 3 Port B Input Data Register PBPIN PBPIN indicates the states of the port B pins Bit Bit Name Initial Value R W Description 7 PB7PIN Undefined R 6 PB6PIN Undefined R 5 PB5PIN Undefined R 4...

Page 380: ...te is fetched into PBDR at the sampling cycle set by NCCS The operation changes according to the other control bits See section 8 2 11 7 Pin Functions for details 5 Noise Canceler Mode Control Registe...

Page 381: ...alue is read from these bits 2 1 0 NCCK2 NCCK1 NCCK0 0 0 0 R W R W R W These bits set the sampling cycle of the noise cancelers When 34 MHz 000 0 06 s 2 100 963 8 s 32768 001 0 94 s 32 101 1 9 ms 6553...

Page 382: ...tched as shown below according to the PBnDDR bit When using this pin as the EVENT input pin clear the PBnDDR bit to 0 These pins can be used as EtherC I O pins when the EtherC is enabled EtherC E DMAC...

Page 383: ...ion is switched as shown below according to the combination of the module stop state in the EtherC and E DMAC and the PBnDDR bit EtherC E DMAC Either of them is stopped Both of them are stopped PBnDDR...

Page 384: ...utput data register PCODR Port C input data register PCPIN 1 Port C Data Direction Register PCDDR The individual bits of PCDDR specify input or output for the port C pins Bit Bit Name Initial Value R...

Page 385: ...general output port 3 Port C Input Data Register PCPIN PCPIN indicates the pin states of port C Bit Bit Name Initial Value R W Description 7 PC7PIN Undefined R 6 PC6 PIN Undefined R 5 PC5PIN Undefined...

Page 386: ...nd IIC_2 IIC_3 and IIC_4 input output pins The relationship between register setting values and pin functions are as follows PC7 The PC7 pin functions as a bus control output pin PC6 When set for 16 b...

Page 387: ...1 PC5DDR 0 1 X Pin function PC5 input pin PC5 output pin SDA4 input output pin Legend X Don t care PC4 SCL4 The pin function is switched as shown below according to the combination of the ICE bit in I...

Page 388: ...nd X Don t care PC1 SDA2 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of the IIC_2 and the PC1DDR bit ICE 0 1 PC1DDR 0 1 X Pin function PC1 input pin...

Page 389: ...register PDPIN 1 Port D Data Direction Register PDDDR The individual bits of PDDDR specify input or output for the port D pins Bit Bit Name Initial Value R W Description 7 PD7DDR 0 W 6 PD6DDR 0 W 5 P...

Page 390: ...general output port 3 Port D Input Data Register PDPIN PDPIN indicates the pin states of port D Bit Bit Name Initial Value R W Description 7 PD7PIN Undefined R 6 PD6 PIN Undefined R 5 PD5PIN Undefined...

Page 391: ...of the ICE bit in ICCR of the IIC_5 and the PD7DDR bit ICE 0 1 PD7DDR 0 1 X Pin function PD7 input pin PD7 output pin SDA5 input output pin Legend X Don t care PD6 SCL5 The pin function is switched as...

Page 392: ...o the combination of the FGA20E bit in HICR0 of the LPC and the PD3DDR bit FGA20E 0 1 PD3DDR 0 1 0 Pin function PD3 input pin PD3 output pin GA20 output pin PD2 PME The pin function is switched as sho...

Page 393: ...tware This input pull up MOS can be used in any operating mode and can be specified as on or off on a bit by bit basis PDnDDR 0 1 PDnODR 1 0 X PDn pull up MOS ON OFF OFF Legend n 5 to 0 X Don t care T...

Page 394: ...r PEPIN 1 Port E Data Direction Register PEDDR The individual bits of PEDDR specify input or output for the port E pins Bit Bit Name Initial Value R W Description 7 PE7DDR 0 W 6 PE6DDR 0 W 5 PE5DDR 0...

Page 395: ...neral output port 3 Port E Input Data Register PEPIN PEPIN indicates the pin states of port E Bit Bit Name Initial Value R W Description 7 PE7PIN Undefined R 6 PE6PIN Undefined R 5 PE5PIN Undefined R...

Page 396: ...abled or disabled and the PE7DDR bit LPC Disabled Enabled PE7DDR 0 1 X Pin function PE7 input pin PE7 output pin SERIRQ input output pin Legend X Don t care PE6 LCLK The pin function is switched as sh...

Page 397: ...nd the PE3DDR bit LPC Disabled Enabled PE3DDR 0 1 X Pin function PE3 input pin PE3 output pin LAD3 input output pin Legend X Don t care PE2 LAD2 The pin function is switched as shown below according t...

Page 398: ...REJ09B0403 0100 PE0 LAD0 The pin function is switched as shown below according to whether the LPC is enabled or disabled and the PE0DDR bit LPC Disabled Enabled PE0DDR 0 1 X Pin function PE0 input pin...

Page 399: ...eset and retains the value even if an internal reset signal of the WDT is generated Bit Bit Name Initial Value R W Description 7 Reserved 6 PF6DDR 0 W When set to 1 the corresponding pin functions as...

Page 400: ...he general output port 3 Port F Input Data Register PFPIN PFPIN indicates the pin states of port F Bit Bit Name Initial Value R W Description 7 Reserved Undefined value is read from this bit 6 PF6PIN...

Page 401: ...ion PF6 input pin PF6 output pin ExPWX2 output pin Legend X Don t care PF1 RS9 MDC The pin function is switched as shown below according to the combination of the module stop state in the EtherC and e...

Page 402: ...h peripheral function description the original pin name is used 8 3 1 IRQ Sense Port Select Register 16 ISSR16 IRQ Sense Port Select Register ISSR ISSR16 and ISSR select pins for the IRQ15 to IRQ0 inp...

Page 403: ...6 is selected 1 PA6 ExIRQ6 is selected 5 ISS5 0 R W 0 P45 IRQ5 is selected 1 PA5 ExIRQ5 is selected 4 ISS4 0 R W 0 P44 IRQ4 is selected 1 PA4 ExIRQ4 is selected 3 ISS3 0 R W 0 P43 IRQ3 is selected 1 P...

Page 404: ...rnal connection of TxD3 and RxD3 with the SCI_3 as the smart card interface 0 TxD3 and RxD3 are not internally connected 1 TxD3 and RxD3 are internally connected 5 4 All 0 R W Reserved The initial val...

Page 405: ...be set equal to T 64 or T 256 where T is the resolution Sixteen operation clocks by combination of eight resolution settings and two base cycle settings Figure 9 1 shows a block diagram of the PWM D...

Page 406: ...timer pulse output of PWMX_1 channel A PWMX output pin 3 PWX3 Output PWM timer pulse output of PWMX_1 channel B 9 3 Register Descriptions The PWMX D A module has the following registers For details o...

Page 407: ...pper two bits DACNT cannot be accessed in 8 bit units DACNT should always be accessed in 16 bit units For details see section 9 4 Bus Master Interface DACNT Bit Bit Name Initial Value R W Description...

Page 408: ...le the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform and to decide whether to output a fine adjustment pulse equal in width to the resoluti...

Page 409: ...be set within a range that depends on the CFS bit If the DADR value is outside this range the PWM output is held constant A channel can be operated with 12 bit precision by fixing DA0 and DA1 to 0 The...

Page 410: ...B Enables or disables output on PWMX D A channel B 0 PWMX D A channel B output at the PWX1 PWX3 pins is disabled 1 PWMX D A channel B output at the PWX1 PWX3 pins is enabled 2 OEA 0 R W Output Enable...

Page 411: ...ects a clock cycle with the CKS bit of DACR of PWMX_1 being 1 See table 9 2 2 1 0 0 R W R W Reserved The initial value should not be changed 0 PWCKX0C 0 R W PWMX_0 Clock Select This bit selects a cloc...

Page 412: ...alue are combined and the combined 16 bit value is written in the register Read When the upper byte is read from the upper byte value is transferred to the CPU and the lower byte value is transferred...

Page 413: ...o DA0 in DADR value corresponds to the total width TH of the high 1 output pulses Figures 9 3 and 9 4 show the types of waveform output available tf tL T Resolution TL tLn OS 0 When CFS 0 m 256 When C...

Page 414: ...to H 00FF Data value T DA13 to 0 H 0100 to H 3FFF 10 0 0 0 0 0 060 ms 1 15 06 s 0 964 ms 14 0 964 ms 66 4 kHz 12 0 0 0 241 ms 0 06 2 Always low high output DA13 to 0 H 0000 to H 003F Data value T DA1...

Page 415: ...ms 1 7 71 ms 493 45 ms 14 493 45 ms 129 7 Hz 12 0 0 123 36 ms 30 12 1024 Always low high output DA13 to 0 H 0000 to H 003F Data value T DA13 to 0 H 0040 to H 3FFF 10 0 0 0 0 30 84 ms 1 0 1 1 0 7 71 m...

Page 416: ...55 tL256 1 conversion cycle tf1 tf2 tf3 tf255 tf256 T 64 tL1 tL2 tL3 tL255 tL256 TL tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tL1 tL2 tL3 tL63 tL64 TL a CF...

Page 417: ...on T 256 and OS 1 inverted PWM output is described below When CFS 1 the upper eight bits DA13 to DA6 in DADR determine the duty cycle of the base pulse while the subsequent six bits DA5 to DA0 determi...

Page 418: ...to be added to the base pulse 1 conversion cycle Base pulse High width 2 256 T Base pulse 2 256 T Additional pulse 1 256 T Base cycle Base cycle Base cycle No 1 No 0 No 63 Additional pulse output loca...

Page 419: ...1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1...

Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...

Page 421: ...8 or 32 can be selected Two independent comparators Counter clearing The free running counters can be cleared on compare match A Three independent interrupts Two compare match interrupts and one over...

Page 422: ...e match B Overflow Clear TIER TCR TOCR Interrupt signal Legend OCRA OCRB OCRAR OCRAF FRC TCSR TIER TCR TOCR Output compare registers A and B 16 bits Output compare registers AR and AF 16 bits Free run...

Page 423: ...C FRC is a 16 bit readable writable up counter The clock source is selected by bits CKS1 and CKS0 in TCR FRC can be cleared by compare match A When FRC overflows from H FFFF to H 0000 the overflow fla...

Page 424: ...added alternately to OCRA and the result is written to OCRA The write operation is performed on the occurrence of compare match A In the 1st compare match A after setting the OCRAMS bit to 1 OCRAF is...

Page 425: ...FA in TCSR is set to 1 0 OCIA requested by OCFA is disabled 1 OCIA requested by OCFA is enabled 2 OCIBE 0 R W Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B req...

Page 426: ...aring condition Read OCFA when OCFA 1 then write 0 to OCFA 2 OCFB 0 R W Output Compare Flag B Indicates that the FRC value matches the OCRB value Setting condition When FRC OCRB Clearing condition Rea...

Page 427: ...t capture signals enables the input capture buffer mode and selects the FRC clock source Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 and cannot b...

Page 428: ...Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF 0 The normal operating mode is specified for OCRA 1 The operating mode using OCRAR and OCRAF...

Page 429: ...crement Timing with Internal Clock Source 10 3 2 Output Compare Output Timing A compare match signal occurs at the last state when the FRC and OCR values match at the timing when the FRC updates the c...

Page 430: ...put compare flag OCFA or OCFB is set to 1 by a compare match signal generated when the FRC value matches the OCRA or OCRB value This compare match signal is generated at the last state in which the tw...

Page 431: ...B0403 0100 10 3 5 Timing of FRC Overflow Flag OVF Setting The FRC overflow flag OVF is set to 1 when FRC overflows changes from H FFFF to H 0000 Figure 10 6 shows the timing of setting the OVF flag Ov...

Page 432: ...atic Addition Timing 10 4 Interrupt Sources The free running timer can request three interrupts OCIA OCIB and FOVI Each interrupt can be enabled or disabled by an enable bit in TIER Independent signal...

Page 433: ...f an internal counter clear signal is generated during the state after an FRC write cycle the clear signal takes priority and the write is not performed Figure 10 8 shows the timing for this type of c...

Page 434: ...If an FRC increment pulse is generated during the state after an FRC write cycle the write takes priority and FRC is not incremented Figure 10 9 shows the timing for this type of conflict Address FRC...

Page 435: ...f OCRAR and OCRAF to OCRA is selected and a compare match occurs in the cycle following the OCRA OCRAR and OCRAF write cycle the OCRA OCRAR and OCRAF write takes priority and the compare match signal...

Page 436: ...FRC Operation When the internal clock is changed the changeover may source FRC to increment This depends on the time at which the clock is switched bits CKS1 and CKS0 are rewritten as shown in table 1...

Page 437: ...ns of CKS1 and CKS0 Bits FRC Operation 1 Switching from low to low Clock before switchover Clock after switchover FRC clock FRC CKS bit rewrite N N 1 2 Switching from low to high Clock before switchov...

Page 438: ...00 No Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N 1 CKS bit rewrite N 2 Note Genera...

Page 439: ...TMR_Y TMR_X The counter input clock can be selected from three internal clocks Selection of two ways to clear the counters The counters can be cleared on compare match A and compare match B Cascading...

Page 440: ...B_1 TCORB_1 TCSR_1 TCR_1 TCNT_0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 Select clock Control logic Internal bus Legend Interrupt signals Clear 0 TMR_1 2 8 64 128 1024 2048 TCORA_0 TCOR...

Page 441: ...elect clock Control logic Internal bus Legend Interrupt signals Clear Y TMR_X 2 4 TMR_Y 4 256 2048 CMIAX CMIBX OVIX CMIAY CMIBY OVIY TCORA_Y TCORB_Y TCNT_Y TCSR_Y TCR_Y TCORA_X TCORB_X TCNT_X TCSR_X T...

Page 442: ...witched by the TMRX Y bit in TCONRS TCONRS is only provided for TMR_X 11 2 1 Timer Counter TCNT Each TCNT is an 8 bit readable writable up counter TCNT_0 and TCNT_1 comprise a single 16 bit register s...

Page 443: ...TMRX Y bit in TCONRS is 1 TCORA_X can be accessed when the TMRX Y bit in TCONRS is 0 See section 11 2 6 Timer Connection Register S TCONRS 11 2 3 Time Constant Register B TCORB TCORB is an 8 bit read...

Page 444: ...6 CMIEA 0 R W Compare Match Interrupt Enable A Selects whether the CMFA interrupt request CMIA is enabled or disabled when the CMFA flag in TCSR is set to 1 0 CMFA interrupt request CMIA is disabled...

Page 445: ...internal clock 64 0 1 0 1 Increments at falling edge of internal clock 32 0 1 1 0 Increments at falling edge of internal clock 1024 0 1 1 1 Increments at falling edge of internal clock 256 1 0 0 X Inc...

Page 446: ...X X Setting prohibited Note If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare match signal simultaneously a count up clock cannot be...

Page 447: ...CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT_0 and TCORA_0 match Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA 5 OVF 0 R W T...

Page 448: ...CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT_1 and TCORA_1 match Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA 5 OVF 0 R W T...

Page 449: ...Clearing condition Read CMFB when CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT_Y and TCORA_Y match Clearing condition Read CMFA when CMFA 1 t...

Page 450: ...Clearing condition Read CMFB when CMFB 1 then write 0 in CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT_X and TCORA_X match Clearing condition Read CMFA when CMFA 1 t...

Page 451: ...0 The TMR_X registers are accessed at addresses H FFFFF0 to H FFFFF5 1 The TMR_Y registers are accessed at addresses H FFFFF0 to H FFFFF5 6 to 0 All 0 R W Reserved The initial values should not be ch...

Page 452: ...and CMFB Setting at Compare Match The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCNT and TCOR values match The compare match signal is generated at the las...

Page 453: ...and CCLR0 bits in TCR Figure 11 5 shows the timing of clearing the counter by a compare match N H 00 Compare match signal TCNT Figure 11 5 Timing of Counter Clear by Compare Match 11 3 4 Timing of Ov...

Page 454: ...s The CMF flag in TCSR_1 is set to 1 when a lower 8 bit compare match occurs Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match the 16 bi...

Page 455: ...nterrupt sources Table 11 3 Interrupt Sources of 8 Bit Timers TMR_0 TMR_1 TMR_Y and TMR_X Channel Name Interrupt Source Interrupt Flag DTC Activation Interrupt Priority TMR_X CMIAX TCORA_X compare mat...

Page 456: ...er Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 11 7 the counter clear takes priority and the write is not performed Address TCNT address I...

Page 457: ...f a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 11 8 the write takes priority and the counter is not incremented Address TCNT address Internal write sign...

Page 458: ...match occurs during the T2 state of a TCOR write cycle as shown in figure 11 9 the TCOR write takes priority and the compare match signal is disabled Address TCOR address Internal write signal TCNT TC...

Page 459: ...k switching causes a change from high to low level as shown in no 3 in table 11 4 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge and TCNT is incremented Errone...

Page 460: ...switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 Notes 1 Includes switching from low to stop and from stop to low 2 Includes switching from stop to high 3 Includes switching from high to stop 4 Ge...

Page 461: ...T can be used as an interval timer In interval timer operation an interval timer interrupt is generated each time the counter overflows A block diagram of the WDT_0 and WDT_1 are shown in figure 12 1...

Page 462: ..._1 Timer control status register_1 TCNT_1 Timer counter_1 Notes 1 The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT...

Page 463: ...prescaler counter 12 3 Register Descriptions The WDT has the following registers To prevent accidental overwriting TCSR and TCNT have to be written to in a method different from normal registers For...

Page 464: ...VF is cleared automatically by the internal reset Clearing conditions When TCSR is read when OVF 1 then 0 is written to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the...

Page 465: ...lock Select 2 to 0 Select the clock source to be input to TCNT The overflow period for 34 MHz is enclosed in parentheses 000 2 period 15 1 s 001 64 period 481 9 s 010 128 period 963 8 s 011 512 period...

Page 466: ...en to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer 0 Interval timer mode 1 Watchdog timer mode 5 TME 0 R W Timer E...

Page 467: ...e 15 1 s 001 64 cycle 481 9 s 010 128 cycle 963 8 s 011 512 cycle 3 856 ms 100 2048 cycle 15 42 ms 101 8192 cycle 61 68 ms 110 32768 cycle 246 7 ms 111 131072 cycle 986 9 ms When PSS 1 000 SUB 2 cycle...

Page 468: ...d for 518 system clocks and the low level signal is simultaneously output from the RESO pin for 132 states as shown in figure 12 2 If the RST NMI bit is cleared to 0 when the TCNT overflows an NMI int...

Page 469: ...e H 00 to TCNT WT IT 1 TME 1 Write H 00 to TCNT 518 system clocks Internal reset signal WT IT TME OVF Overflow OVF 1 Timer mode select bit Timer enable bit Overflow flag Note After the OVF bit becomes...

Page 470: ...an be generated at intervals When the TCNT overflows in interval timer mode an interval timer interrupt WOVI is requested at the same time the OVF bit of TCSR is set to 1 The timing is shown in figure...

Page 471: ...t the same time the low level signal is output from the RESO pin The timing is shown in figure 12 5 TCNT H FF H 00 132 states 518 states Overflow signal internal signal OVF RESO signal Internal reset...

Page 472: ...upt WOVI The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR OVF must be cleared to 0 in the interrupt handling routine When the NMI interrupt request is selected in wa...

Page 473: ...r instruction TCNT and TCSR both have the same write address Therefore satisfy the relative condition shown in figure 12 6 to write to TCNT or TCSR To write to TCNT the higher bytes must contain the v...

Page 474: ...T2 TCNT write cycle Counter write data Figure 12 7 Conflict between TCNT Write and Increment 12 6 3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is o...

Page 475: ...watchdog timer by clearing the TME bit to 0 before switching the mode 12 6 6 System Reset by RESO Signal Inputting the RESO output signal to the RES pin of this LSI prevents the LSI from being initia...

Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...

Page 477: ...enhanced asynchronous communication function 13 1 Features Choice of asynchronous or clock synchronous serial communication mode Full duplex communication capability The transmitter and receiver are...

Page 478: ...reak detection Break can be detected by reading the RxD pin level directly in case of a framing error Clock Synchronous Mode Data length 8 bits Receive error detection Overrun errors Smart Card Interf...

Page 479: ...ception control Baud rate generator BRR Module data bus RDR TSR RSR Parity generation Parity check Legend RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit...

Page 480: ...when smart card interface is selected 3 TxD3 Output Channel 3 transmit data output Note Pin names SCK RxD and TxD are used in the text for all channels omitting the channel designation 13 3 Register...

Page 481: ...for only once RDR cannot be written to by the CPU 13 3 3 Transmit Data Register TDR TDR is an 8 bit register that stores transmit data When the SCI detects that TSR is empty it transfers the transmit...

Page 482: ...mode a fixed data length of 8 bits is used 5 PE 0 R W Parity Enable enabled only in asynchronous mode When this bit is set to 1 the parity bit is added to transmit data before transmission and the pa...

Page 483: ...GSM Mode Setting this bit to 1 allows GSM mode operation In GSM mode the TEND set timing is put forward to 11 0 etu from the start and the clock output control function is appended For details see sec...

Page 484: ...lock cycles S 256 For details see section 13 7 4 Receive Data Sampling Timing and Reception Margin S is described in section 13 3 9 Bit Rate Register BRR 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0...

Page 485: ...rrupt request is enabled 6 RIE 0 R W Receive Interrupt Enable When this bit is set to 1 RXI and ERI interrupt requests are enabled 5 TE 0 R W Transmit Enable When this bit is set to 1 transmission is...

Page 486: ...source and SCK pin function Asynchronous mode 00 Internal clock SCK pin functions as I O port 01 Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin 1x External clock...

Page 487: ...e When this bit is set to 1 reception is enabled 3 MPIE 0 R W Multiprocessor Interrupt Enable enabled only when the MP bit in SMR is 1 in asynchronous mode Write 0 to this bit in smart card interface...

Page 488: ...ates whether TDR contains transmit data Setting conditions When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write Clearing conditions When 0 is written to...

Page 489: ...g condition When a parity error is detected during reception Clearing condition When 0 is written to PER after reading PER 1 2 TEND 1 R Transmit End Setting conditions When the TE bit in SCR is 0 When...

Page 490: ...F 0 R W 1 Receive Data Register Full Indicates whether the receive data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR Clearing...

Page 491: ...fied time passed after the start of 1 byte data transfer The set timing depends on the register setting as follows When GM 0 and BLK 0 2 5 etu 2 after transmission start When GM 0 and BLK 1 1 5 etu 2...

Page 492: ...valid only when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Smart Card Data Invert Speci...

Page 493: ...2n 1 106 Clock synchronous mode B 8 2 N 1 2n 1 106 Smart card interface mode B S 2 N 1 2n 1 106 Error B S 2 N 1 1 100 2n 1 106 Legend B Bit rate bit s N BRR setting for baud rate generator 0 N 255 Op...

Page 494: ...1 64 0 16 1 80 0 47 1 110 0 29 4800 0 129 0 16 0 162 0 15 0 220 0 16 9600 0 64 0 16 0 80 0 47 0 110 0 29 19200 0 32 1 36 0 40 0 76 0 54 0 62 31250 0 19 0 00 0 24 0 00 0 33 0 00 38400 0 15 1 73 0 19 1...

Page 495: ...MHz 20 24 34 Bit Rate bit s n N n N n N 110 250 500 1 k 2 5 k 2 124 2 149 2 212 5 k 1 249 2 74 2 105 10 k 1 124 1 149 1 212 25 k 0 199 0 239 1 84 50 k 0 99 0 119 0 169 100 k 0 49 0 59 0 84 250 k 0 19...

Page 496: ...33 3 25 4 1667 4166666 7 34 5 6667 5666666 7 Table 13 8 BRR Settings for Various Bit Rates Smart Card Interface Mode n 0 s 372 Operating Frequency MHz 20 00 21 4272 25 34 Bit Rate bit s n N Error n N...

Page 497: ...o the space state low level recognizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmi...

Page 498: ...e 13 10 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit da...

Page 499: ...h bit as shown in figure 13 3 Thus the reception margin in asynchronous mode is determined by formula 1 below M 0 5 1 F L 0 5 F 100 Formula 1 2N 1 N D 0 5 M N D L F Reception margin Ratio of bit rate...

Page 500: ...CKE0 bits in SCR When an external clock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the...

Page 501: ...pplied even during initialization Wait Initialization completion Start initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in...

Page 502: ...order start bit transmit data parity bit or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE f...

Page 503: ...nabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation proc...

Page 504: ...red to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 4 If a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive data...

Page 505: ...PER and RDRF bits to 0 before resuming reception Figure 13 9 shows a sample flowchart for serial data reception Table 13 11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER FER PER...

Page 506: ...ror processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by read...

Page 507: ...8 REJ09B0403 0100 End 3 Error processing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Bre...

Page 508: ...nsmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data wit...

Page 509: ...Receiving station D ID 01 ID 02 ID 03 ID 04 Serial communication line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station s...

Page 510: ...SCI initialization The TxD pin is automatically designated as the transmit data output pin After the TE bit is set to 1 a frame of 1s is output and transmission is enabled 2 SCI status check and tran...

Page 511: ...Data 1 MPB Stop bit Data ID2 Start bit Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared t...

Page 512: ...n and comparison Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 ag...

Page 513: ...465 of 1178 REJ09B0403 0100 End Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR...

Page 514: ...duplex communication by use of a common clock Both the transmitter and the receiver also have a double buffered structure so that the next transmit data can be written during transmission or the prev...

Page 515: ...alization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elaps...

Page 516: ...s generated Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished continuous transmission can be enabled 3 8 bit data is...

Page 517: ...clear the receive error flags to 0 before starting transmission Note that clearing the RE bit to 0 does not clear the receive error flags Transfer direction Bit 0 Serial data Synchronization clock 1...

Page 518: ...he transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmiss...

Page 519: ...ains to be set to 1 3 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request...

Page 520: ...the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Rea...

Page 521: ...tions To switch from transmit mode to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1 clear the TE bit in S...

Page 522: ...on reception cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the R...

Page 523: ...smission reception allowing self diagnosis To supply the IC card with the clock pulses generated by the SCI input the SCK pin output to the CLK pin of the IC card A reset signal can be supplied via th...

Page 524: ...ct convention and inverse convention types follow the procedure below Ds A Z Z A Z Z Z Z A A Z Z state D0 D1 D2 D3 D4 D5 D6 D7 Dp Figure 13 23 Direct Convention SDIR SINV O E 0 For the direct conventi...

Page 525: ...the O E bit in SMR to invert the parity bit in both transmission and reception 13 7 3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respe...

Page 526: ...s mode At reception the falling edge of the start bit is sampled using the internal basic clock in order to perform internal synchronization Receive data is sampled at the 16th 32nd 186th and 128th ri...

Page 527: ...Clear the TE and RE bits in SCR to 0 2 Clear the error flags ORER ERS and PER in SSR to 0 3 Set the GM BLK O E BCP1 BCP0 CKS1 and CKS0 bits in SMR appropriately Also set the PE bit to 1 4 Set the SMI...

Page 528: ...g automatic data retransmission 3 If no error signal is returned from the receiving end the ERS bit in SSR is not set to 1 In this case one frame of data is determined to have been transmitted includi...

Page 529: ...R to TSR Transfer from TDR to TSR 2 3 3 Figure 13 26 Data Re transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR whic...

Page 530: ...B0403 0100 Initialization No Yes Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing T...

Page 531: ...ally performed using an RXI interrupt request to activate the DTC In reception setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1 This activates DT...

Page 532: ...Page 484 of 1178 REJ09B0403 0100 Initialization Read data from RDR and clear RDRF flag in SSR to 0 Clear RE bit in SCR to 0 Start reception Start Error processing No No No Yes Yes ORER 0 and PER 0 RD...

Page 533: ...width SCK CKE0 Specified pulse width Figure 13 31 Clock Output Fixing Timing At power on and transitions to from software standby mode use the following procedure to secure the appropriate clock duty...

Page 534: ...to the value for the output fixed state in software standby mode 3 Write 0 to the CKE0 bit in SCR to stop the clock 4 Wait for one cycle of the serial clock In the mean time the clock output is fixed...

Page 535: ...PER or FER flag in SSR is set to 1 an ERI interrupt request is generated An RXI interrupt can activate the DTC to allow data transfer The RDRF flag is automatically cleared to 0 at data transfer by t...

Page 536: ...and TEND flags are automatically cleared to 0 at data transfer by the DTC If an error occurs the SCI automatically re transmits the same data During re transmission the TEND flag remains as 0 thus not...

Page 537: ...a transmission To maintain the communication line at mark state until TE is set to 1 set both DDR and DR to 1 Since the TE bit is cleared to 0 at this point the TxD pin becomes an I O port and 1 is ou...

Page 538: ...ore allowing the transmit clock to be input If the transmit clock is input within four clock cycles after TDR modification the SCI may malfunction figure 13 33 When using the DTC to read RDR be sure t...

Page 539: ...data being transmitted will be undefined To transmit data in the same transmission mode after mode cancellation set TE to 1 read SSR write to TDR clear TDRE in this order and then start transmission T...

Page 540: ...DR and clearing TDRE to 0 after mode cancellation however if the DTC has been initiated the data remaining in DTC RAM will be transmitted when TE and TIE are set to 1 2 Also clear TIE and TEIE to 0 wh...

Page 541: ...ote Initialized in software standby mode Figure 13 36 Pin States during Transmission in Clock Synchronous Mode Internal Clock Reception Before making the transition to module stop or software standby...

Page 542: ...o No Yes Yes Read receive data in RDR Read RDRF flag in SSR Make transition to software standby mode etc Cancel software standby mode etc RE 0 Initialization RE 1 2 Change operating mode RDRF 1 1 Data...

Page 543: ...e 13 38 SCK Port CKE0 CKE1 C A TE Data 1 Transmission end 2 TE 0 3 C A 0 4 Low pulse output Bit 6 Bit 7 Low pulse of half a cycle Figure 13 38 Switching from SCK Pins to Port Pins To prevent the low p...

Page 544: ...Rev 1 00 Mar 12 2008 Page 496 of 1178 REJ09B0403 0100 SCK Port CKE0 CKE1 C A TE Data 1 Transmission end 2 TE 0 4 C A 0 3 CKE1 1 5 CKE1 0 Bit 6 Bit 7 High output Figure 13 39 Prevention of Low Pulse O...

Page 545: ...CRC operation circuit are listed below CRC code generated for any desired data length in an 8 bit unit CRC operation executed on eight bits in parallel One of three generating polynomials selectable...

Page 546: ...R to H 0000 6 to 3 All 0 R Reserved The initial value should not be changed 2 LMS 0 R W CRC Operation Switch Selects CRC code generation for LSB first or MSB first communication 0 Performs CRC operati...

Page 547: ...r When bits 1 and 0 in CRCCR are set to G1 0 and G0 1 respectively the lower byte of this register contains the result 14 3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC co...

Page 548: ...0 7 0 7 0 7 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDIR CRCDORH CRCDORL CRC code generation 2 Write H F0 to CRCDIR 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 CRC code H EF1F CRC code Output Dat...

Page 549: ...1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 CRCDIR CRCDORH CRCDORL CRC code generation 4 Write H 8F to CRCDIR 1 7 0 0 0 1 1 0 7 0 7 0 7 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 CRCDIR CRCDORH CRCDORL CRC c...

Page 550: ...1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 CRCDIR CRCDORH CRCDORL CRC code generation 4 Write H EF to CRCDIR 1 7 1 1 0 1 1 0 7 0 7 0 7 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 CRCDIR CRCDORH CRCDORL CRC c...

Page 551: ...SB first transmission CRCDIR CRCDORH CRCDORL 1 CRC code generation 2 Transmission data i LSB first transmission CRC code generation After specifying the operation method write data to CRCDIR in the se...

Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...

Page 553: ...de efficient high speed continuous communication In addition the SCIF can be connected to the LPC interface for direct control from the LPC host 15 1 Features Full duplex communication The transmitter...

Page 554: ...clock SCIFCR FIER FIIR FFCR FLCR FMCR FLSR FMSR FSCR Register transmission reception control SCIF interrupt request System clock LCLK Receive FIFO 16 bytes Reception 1 byte Legend FRSR Receive shift r...

Page 555: ...s Table 15 1 Pin Configuration Pin Name Port Input Output Function TxDF P50 Output Transmit data output RxDF P51 Input Receive data input RI P25 Input Ring indicator input DCD P24 Input Data carrier d...

Page 556: ...r FTHR Divisor latch L FDLL Interrupt enable register FIER Divisor latch H FDLH Interrupt identification register FIIR FIFO control register FFCR Line control register FLCR Modem control register FMCR...

Page 557: ...be read before the next data is received If new data is received before the remaining data is read the data is overwritten resulting in an overrun error When this register is read with the FIFO enable...

Page 558: ...with the FIFO full the written data is lost Bit Bit Name Initial Value R W Description 7 to 0 Bit 7 to bit 0 W Stores serial data to be transmitted The data is 16 bytes when the FIFO is enabled 15 3...

Page 559: ...e should not be changed 3 EDSSI 0 R W Modem Status Interrupt Enable 0 Modem status interrupt disabled 1 Modem status interrupt enabled 2 ELSI 0 R W Receive Line Status Interrupt Enable 0 Receive line...

Page 560: ...etting 00 Transmit receive FIFOs disabled 11 Transmit receive FIFOs enabled 5 4 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 3 2 1 INTID2 INTID1 INTID0 0 0...

Page 561: ...Receive line status Overrun error parity error framing error break interrupt FLSR read 0 1 0 0 2 Receive data ready Receive data remaining FIFO trigger level FRBR read or receive FIFO is below trigger...

Page 562: ...e 01 4 bytes 10 8 bytes 11 14 bytes 5 4 Reserved These bits cannot be modified 3 DMAMODE 0 DMA Mode This bit is not supported The initial value should not be changed 2 XMITFRST 0 W Transmit FIFO Reset...

Page 563: ...access enabled 6 BREAK 0 R W Break Control Generates a break by driving the serial output signal TxDF low The break state is released by clearing this bit 0 Break released 1 Break generated 5 STICK PA...

Page 564: ...odem Control Register FMCR FMCR controls output signals Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 4 LOO...

Page 565: ...t 0 Interrupt disabled 1 Interrupt enabled Loopback test Internally connected to the DCD input pin 2 OUT1 0 R W OUT1 Normal operation No effect on operation Loopback test Internally connected to the R...

Page 566: ...at could cause an error after an FIFO clear 1 A receive FIFO error Setting condition When at least one data error parity error framing error or break interrupt has occurred in the FIFO 6 TEMT 1 R Tran...

Page 567: ...ansmit data remains in FTHR Clearing condition Transmit data is written to FTHR 1 No transmit data in FTHR Setting condition When data transfer from FTHR to FTSR is completed 4 BI 0 R Break Interrupt...

Page 568: ...sumes that the framing error is due to the next start bit samples the start bit and treats it as a start bit 0 No framing error Clearing condition FLSR read 1 A framing error Setting condition Invalid...

Page 569: ...ror occurs and the previous data is lost When the FIFO is enabled When the FIFO is full and reception of the next data has been completed an overrun error occurs The FIFO data is retained but the last...

Page 570: ...erted state of the DSR input pin 4 CTS 0 R Clear to Send Indicates the inverted state of the CTS input pin 3 DDCD 0 R Delta Data Carrier Indicator Indicates a change in the DCD input signal after the...

Page 571: ...after FMSR read Setting condition A change in the DSR input signal 0 DCTS 0 R Delta Clear to Send Indicator Indicates a change in the CTS input signal after the DCTS bit is read 0 No change in the CTS...

Page 572: ...LPC For details see table 15 4 5 0 R W Reserved Do not change the initial value 4 OUT2LOOP 0 R W Enables or disables interrupts during a loopback test 0 Interrupt enabled 1 Interrupt disabled 3 2 CKS...

Page 573: ...tput Setting Bit SCIFE in HICR5 0 1 SCIFOE1 0 1 0 1 SCIFOE0 0 1 0 1 0 1 0 1 P65 pin PORT PORT RTS PORT RTS PORT RTS PORT P27 pin PORT PORT DTR PORT DTR PORT DTR PORT P50 pin PORT PORT TxDF TxDF TxDF T...

Page 574: ...of Baud Rate Settings 00 01 CKSEL1 CKSEL0 LCLK 33 MHz divided by 18 System Clock 34 MHz divided by 11 Baud rate FDLH FDLL Hex Error FDLH FDLL Hex Error 50 0900 0 54 H 0F18 0 01 75 0600 0 54 H 0A10 0 0...

Page 575: ...on line and when it detects the space state low level recognizes a start bit and starts serial communication Inside the SCIF the transmitter and receiver are independent units enabling full duplex com...

Page 576: ...s No Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR Set the SCIF input output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR Set the DLAB bit in FLCR to 1 to enable access to FDLL a...

Page 577: ...THRE flag in FLSR is 1 and write transmit data to FTHR When FIFOs are used write 1 byte to 16 byte transmit data When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1 an FTHR empty interrup...

Page 578: ...0 1 Confirm that the DR flag in FLSR is 1 to ensure that receive data is in the buffer When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1 a receive data ready interrupt occurs 2 Read the...

Page 579: ...L0 bits in SCIFCR Set the SCIF input output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR 2 Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH 3 The initial value of FDLL and FDLH is 0...

Page 580: ...xample of the data transmission reception standby flowchart No No Yes Transmit data exists Transmission flow Reception flow Yes Initialization 1 2 1 When a receive data ready interrupt occurs go to th...

Page 581: ...ransmission or transmission standby Yes Transmission reception standby 1 2 3 4 1 Confirm that the CTS flag in FMSR is 1 2 Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is em...

Page 582: ...ransmit FIFO Set XMITFRST bit in FFCR to 1 Other processing Prepare for retransmission Transmission flow DCTS 1 No Yes 1 2 3 4 1 Read the DCTS flag in FMSR in the modem status change interrupt process...

Page 583: ...standby flow BI 1 FE 1 PE 1 or OE 1 DR 0 No Yes 1 2 3 4 1 When data is received a receive data ready interrupt occurs Go to the data reception flow by using this interrupt trigger 2 Confirm that the B...

Page 584: ...Read FLSR Set RTS bit in FMCR to 1 Transmission reception standby flow DR 0 No Yes 1 2 3 4 1 When data is received at a trigger level higher than the receive FIFO trigger level specified in the initia...

Page 585: ...interface Table 15 6 shows the correspondence between LPC interface I O address and access to the SCIF registers For details of the LPC interface settings see section 19 LPC interface LPC Table 15 6...

Page 586: ...eset LPC Reset LPC Shutdown LPC Abort SCIFADRH Bits 15 to 8 Initialized Retained Retained Retained SCIFADRL Bits 7 to 0 Initialized Retained Retained Retained HICR5 SCIFE Initialized Retained Retained...

Page 587: ...ady Acceptance of receive data FIFO trigger level Character timeout when FIFO is enabled No data is input to or output from the receive FIFO for the 4 character time period while one or more character...

Page 588: ...Section 15 Serial Communication Interface with FIFO SCIF Rev 1 00 Mar 12 2008 Page 540 of 1178 REJ09B0403 0100...

Page 589: ...e a software bridge for IPMI applications Five serial pin multiplexed modes Mode 0 Each COM port is used for its respective serial communication module COM1 for SCIF COM2 for SCI_1 and COM3 for SCI_3...

Page 590: ...pin multiplexed modes Table 16 1 Pin Configuration Module Symbol I O Function Port Pin SCIF TxDF Output Transmit data P50 RxDF Input Receive data P51 RI Input Ring Indicator detect P25 DCD Input Data...

Page 591: ...0 SMR0 Bit Bit Name Initial Value R W Description 7 DCD1 R Monitors the state of the DCD line in modes 1 3 and 4 6 RI1 R Monitors the state of the RI line in modes 1 3 and 4 5 DSR1 R Monitors the stat...

Page 592: ...nitors the state of the CTS pin of COM1 in mode 1 Monitors the state of the RTS pin of SCIF in mode 2 6 DTR1 1 R W Controls the output on the DTR pin of COM1 in modes 3 and 4 0 0 is output 1 1 is outp...

Page 593: ...nd COM3 with SCI_3 DCD RI DSR DTR CTS RTS RxDF and TxDF of SCIF are connected to the corresponding pins of COM1 Tx Rx of COM1 are tied across to RxDF TxDF cross connection RxD1 and TxD1 of SCI_1 are c...

Page 594: ...d Rx of COM2 is fixed at 1 RxD3 and TxD3 of SCI_3 are cross connected to COM3 The pin states of DCD RI and DSR of COM1 are reflected in bits DCD1 RI1 and DSR1 of the SMR0 register The pin state of CTS...

Page 595: ...ected to TxD1 RxD1 of SCI_1 internally COM2 is not available N A and Rx of COM2 is fixed at 1 RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3 The value written to bit RTS1 of the SMR1 regist...

Page 596: ...SCIF signals are not used DCD RI DSR CTS of SCIF are fixed at 1 RxD3 and TxD3 of SCI_3 are connected to Tx and Rx of COM3 The states of DCD RI DSR of COM1 are reflected in bits DCD1 RI1 DSR1 of the SM...

Page 597: ...he states of DCD RI DSR of COM1 are reflected in bits DCD1 RI1 DSR1 of the SMR0 register and CTS of COM1 is reflected to CTS1 bit of SMR1 register The values written to bits DTR1 RTS1 of the SMR1 regi...

Page 598: ...plex Mode Rev 1 00 Mar 12 2008 Page 550 of 1178 REJ09B0403 0100 16 5 Serial Port Pin Configuration a SME 1 SCI SCIF with serial pin multiplexed mode enabled b SME 0 SCI SCIF with serial pin multiplexe...

Page 599: ...gure 17 1 is a block diagram of the SSU 17 1 Features Choice of SSU mode and clock synchronous mode Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous seri...

Page 600: ...128 256 Clock selector Internal data bus Bus interface SCS SSI Shiftout Shiftin OEI TXI TEI Legend SSCRH SSCRL SSCR2 SSMR SSER SSSR SSTDR0 to SSTDR3 SSRDR0 to SSRDR3 SSTRSR SS control register H SS c...

Page 601: ...lect input output 17 3 Register Descriptions The SSU has the following registers SS control register H SSCRH SS control register L SSCRL SS mode register SSMR SS enable register SSER SS status registe...

Page 602: ...are output from the SSCK pin When the CE bit in SSSR is set this bit is automatically cleared 0 Slave mode is selected 1 Master mode is selected 6 BIDE 0 R W Bidirectional Mode Enable Selects that bo...

Page 603: ...to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction 0 Output level can be changed by the SOL bit 1 Output level cannot be changed by the SOL bit This bit is alway...

Page 604: ...SU mode 1 Clock synchronous mode 5 SRES 0 R W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer After that this bit is automatically cleared The ORER TEND TDRE RDRF and C...

Page 605: ...0 R W Clock Polarity Select Selects the SSCK clock polarity 0 High output in idle mode and low output in active mode 1 Low output in idle mode and high output in active mode 5 CPHS 0 R W Clock Phase S...

Page 606: ...nable When this bit is set to 1 reception is enabled 5 4 All 0 R W Reserved These bits are always read as 0 The initial value should not be changed 3 TEIE 0 R W Transmit End Interrupt Enable When this...

Page 607: ...eived later While ORER 1 consecutive serial reception cannot be continued Serial transmission cannot be continued either Setting condition When one byte of the next reception is completed with RDRF 1...

Page 608: ...ing 0 after reading RDRF 1 When reading receive data from SSRDR 0 CE 0 R W Conflict Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS 0...

Page 609: ...drain output Pins to output serial data differ according to the register setting For details 14 4 3 Relationship between Data Input Output Pins and Shift Register 0 CMOS output 1 NMOS open drain outpu...

Page 610: ...bits are always read as 0 The initial value should not be changed 17 3 7 SS Transmit Data Registers 0 to 3 SSTDR0 to SSTDR3 SSTDR is an 8 bit register that stores transmit data When 8 bit data length...

Page 611: ...n this way consecutive receive operations can be performed Read SSRDR after confirming that the RDRF bit in SSSR is set to 1 SSRDR is a read only register therefore cannot be written to by the CPU 17...

Page 612: ...is selected and the SSCK pin is used as an input pin 17 4 2 Relationship of Clock Phase Polarity and Data The relationship of clock phase polarity and transfer data depends on the combination of the C...

Page 613: ...DE 1 bidirectional mode see figures 17 3 3 and 4 However even if both the TE and RE bits are set to 1 transmission and reception are not performed simultaneously Either the TE or RE bit must be select...

Page 614: ...tionship of communication modes and input output pin functions are shown in tables 17 2 to 17 4 Table 17 2 Communication Modes and Pin States of SSI and SSO Pins Register Setting Pin State Communicati...

Page 615: ...0 0 1 Input 1 0 1 Output 1 0 0 Clock synchronous communication mode 1 Input 1 0 1 Output Legend Not used as SSU pin can be used as I O port Table 17 4 Communication Modes and Pin States of SCS Pin Re...

Page 616: ...0 sets the TDRE bit to 1 clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting initial values 1 2 3 4 End Set a b...

Page 617: ...t is set to 1 clears the TDRE bit in SSSR to 0 and the SSTDR contents are transferred to SSTRSR After that the SSU sets the TDRE bit to 1 and starts transmission At this time if the TIE bit in SSER is...

Page 618: ...7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSO TDRE TEND LSI operation User operation LSI operation User operation LSI o...

Page 619: ...n be written to SSTDR The TDRE bit is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After...

Page 620: ...he SCS pin and a transfer clock is input to the SSCK pin the SSU receives data in synchronization with the transfer clock When 1 frame data has been received the RDRF bit in SSSR is set to 1 and the r...

Page 621: ...Bit 4 Bit 5 Bit 5 Bit 6 Bit 6 Bit 7 Bit 7 LSI operation Dummy read SSRDR0 Dummy read SSRDR0 and SSRDR1 Read SSRDR0 User operation LSI operation User operation LSI operation User operation SSTDR0 LSB...

Page 622: ...ive data in SSRDR 5 To complete reception To complete reception read receive data after clearing the RE bit to 0 When reading SSRDR without clearing the RE bit reception is resumed No Yes Yes No Start...

Page 623: ...eceive error occurs execute the designated error processing after reading the ORER bit in SSSR After that clear the ORER bit to 0 While the ORER bit is set to 1 transmission or reception is not resume...

Page 624: ...pin within the period a conflict error occurs At this time the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0 Note While the CE bit is set to 1 transmission or reception is not resumed Cl...

Page 625: ...0 Although clearing the TE bit to 0 sets the TDRE bit to 1 clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting...

Page 626: ...hat the SSU sets the TDRE bit to 1 and starts transmission At this time if the TIE bit in SSER is set to 1 a TXI interrupt is generated When 1 frame data has been transferred with TDRE 0 the SSTDR con...

Page 627: ...SSTDR The TDRE bit is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After completion of t...

Page 628: ...s set to 1 and the receive data is stored in SSRDR At this time if the RIE bit is set to 1 an RXI interrupt is generated The RDRF bit is automatically cleared to 0 by reading SSRDR When the RDRF bit h...

Page 629: ...ng SSRDR without clearing the RE bit reception is resumed No Yes Yes No Start Initial setting RE 1 reception started Read SSSR RDRF 1 ORER 1 Consecutive data reception Read received data in SSRDR RDRF...

Page 630: ...execute the designated error processing after reading the ORER bit in SSSR After that clear the ORER bit to 0 While the ORER bit is set to 1 transmission or reception is not resumed 5 Procedure for c...

Page 631: ...I vector address the interrupt source should be decided by their flags Table 17 5 lists the interrupt sources When an interrupt condition shown in table 17 5 is satisfied an interrupt is requested Cle...

Page 632: ...Section 17 Synchronous Serial Communication Unit SSU Rev 1 00 Mar 12 2008 Page 584 of 1178 REJ09B0403 0100...

Page 633: ...s format Selection of acknowledge output levels when receiving I 2 C bus format Automatic loading of acknowledge bit when transmitting I 2 C bus format Wait function in master mode I 2 C bus format A...

Page 634: ...ve different specifications for permissible applied voltages For details see section 31 Electrical Characteristics SCL PS ICCR ICXR ICMR ICSR ICDRS SAR SARX SDA ICCR ICMR ICSR ICDR ICXR SAR SARX PS IC...

Page 635: ...7 of 1178 REJ09B0403 0100 SCL in SCL out SDA in SDA out Slave 1 SCL SDA SCL in SCL out SDA in SDA out Slave 2 SCL SDA SCL in SCL out SDA in SDA out Master This LSI SCL SDA VCC VDD VCC SCL SDA Figure 1...

Page 636: ...nnel IIC_1 1 SDA1 Input Output Data input output pin of channel IIC_1 SCL2 Input Output Clock input output pin of channel IIC_2 2 SDA2 Input Output Data input output pin of channel IIC_2 SCL3 Input Ou...

Page 637: ...lly into a shift register ICDRS receive buffer ICDRR and transmit buffer ICDRT Data transfers among the three registers are performed automatically in accordance with changes in the bus state and they...

Page 638: ...1 Receive data bits should be read from the LSB side when MLS 0 and from the MSB side when MLS 1 ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR The initial value of ICD...

Page 639: ...C bus format selected if the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition the LSI operates as the slave device specified...

Page 640: ...at SAR slave address recognized SARX slave address ignored General call address recognized 1 0 I 2 C bus format SAR slave address ignored SARX slave address recognized General call address ignored 1 C...

Page 641: ...edge bit are transferred consecutively with no wait inserted 1 After the fall of the clock for the final data bit 8th clock the IRIC flag is set to 1 in ICCR and a wait state begins with SCL at the lo...

Page 642: ...r frames If bits BC2 to BC0 are set to a value other than B 000 the setting should be made while the SCL line is low The bit counter is initialized to B 000 when a start condition is detected The valu...

Page 643: ...n 7 to 4 Reserved These bits cannot be modified The read values are undefined 3 TCSS 0 R W Transfer Rate Clock Source Select This bit selects a clock rate to be applied to the I 2 C bus transfer rate...

Page 644: ...250 0 kHz 312 5 kHz 425 0 kHz 1 100 200 0 kHz 250 0 kHz 340 0 kHz 1 0 112 178 6 kHz 223 2 kHz 303 6 kHz 1 128 156 3 kHz 195 3 kHz 265 6 kHz 1 0 0 0 56 357 1 kHz 446 4 kHz 607 1 kHz 1 80 250 0 kHz 312...

Page 645: ...160 125 0 kHz 156 3 kHz 212 5 kHz 1 200 100 0 kHz 125 0 kHz 170 0 kHz 1 0 224 89 3 kHz 111 6 kHz 151 8 kHz 1 256 78 1 kHz 97 7 kHz 132 8 kHz 1 0 0 0 112 178 6 kHz 223 2 kHz 303 6 kHz 1 160 125 0 kHz...

Page 646: ...sed 6 IEIC 0 R W I 2 C Bus Interface Interrupt Enable 0 Disables interrupts from the I 2 C bus interface to the CPU 1 Enables interrupts from the I 2 C bus interface to the CPU 5 4 MST TRS 0 0 R W R W...

Page 647: ...t in bus contention in I 2 C bus format master mode TRS setting conditions 1 When 1 is written by software except for TRS clearing condition 3 2 When 1 is written in TRS after reading TRS 0 for TRS cl...

Page 648: ...SDA level changes from high to low under the condition of SCL high assuming that the start condition has been issued BBSY clearing conditions When the SDA level changes from low to high under the cond...

Page 649: ...ceive clock At the end of data transfer rise of the 9th transmit receive clock When a slave address is received after bus mastership is lost If 1 is received as the acknowledge bit when the ACKB bit i...

Page 650: ...condition is detected in transmit mode when a start condition is detected and the ICDRE flag is set to 1 When transmitting the data in the ICDR register buffer when data is transferred from ICDRT to...

Page 651: ...is set the IRTR flag may or may not be set The IRTR flag the DTC start request flag is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after...

Page 652: ...e state 1 1 1 0 0 0 0 0 0 0 1 Transmission end with ICDRE 1 1 1 1 0 0 0 0 0 0 0 0 ICDR write with the above state or after start condition detected 1 1 1 0 0 1 0 0 0 0 0 1 Automatic data transfer from...

Page 653: ...0 1 0 0 0 0 1 1 0 1 1 General call address match in first frame SARX H 00 0 1 0 1 1 0 0 1 1 0 0 0 1 1 SAR match in first frame SAR SARX 0 1 1 0 0 0 1 Transmission end ACKE 1 and ACKB 1 0 1 1 0 0 1 0...

Page 654: ...DR read with the above state 0 0 1 0 0 1 0 2 0 0 0 1 Automatic data transfer from ICDRS to ICDRR with the above state 0 0 1 0 3 0 1 3 0 Stop condition detected Legend 0 0 state retained 1 1 state reta...

Page 655: ...is detected after frame transfer is completed Clearing conditions When 0 is written in STOP after reading STOP 1 When the IRIC flag is cleared to 0 5 IRTR 0 R W I 2 C Bus Interface Continuous Transfe...

Page 656: ...t condition is detected In master mode 3 AL 0 R W Arbitration Lost Flag Indicates that arbitration was lost in master mode Setting conditions When ALSL 0 If the internal SDA and SDA pin disagree at th...

Page 657: ...is written to transmit mode or read from receive mode When 0 is written in AAS after reading AAS 1 In master mode 1 ADZ 0 R W General Call Address Recognition Flag In I 2 C bus format slave receive mo...

Page 658: ...read the value loaded from the bus line returned by the receiving device is read in transmission when TRS 1 In reception when TRS 0 the value set by internal software is read When this bit is written...

Page 659: ...op condition is detected STOP 1 or ESTP 1 in slave mode 1 Disables IRIC flag setting and interrupt generation when the stop condition is detected 6 HNDS 0 R W Handshake Receive Operation Select Enable...

Page 660: ...eived successfully and transferred from ICDRS to ICDRR 1 When data is received successfully while ICDRF 0 at the rise of the 9th clock pulse 2 When ICDR is read successfully in receive mode after data...

Page 661: ...sferred from ICDRT to ICDRS 1 When data is transmitted completely while ICDRE 0 at the rise of the 9th clock pulse 2 When data is written to ICDR completely in transmit mode after data was transmitted...

Page 662: ...ich arbitration is lost 0 If the SDA pin state disagrees with the data that I 2 C bus interface outputs at the rise of SCL and the SCL pin is driven low by another device 1 If the SDA pin state disagr...

Page 663: ...uld not be changed ICSMBCR is enabled to access when bit MSTP4 is cleared to 0 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 SMB5E SMB4E SMB3E SMB2E SMB1E SMB0E 0 0 0 0 0 00 R W R W R W R W R...

Page 664: ...MHz 25 MHz 34 MHz 0 Min 100 80 59 Max 150 120 88 1 0 0 Min 150 120 88 Max 250 200 147 1 Min 200 160 118 Max 350 280 206 1 0 Min 300 240 176 Max 550 440 324 1 Min 500 400 294 Max 950 760 559 Notes n 0...

Page 665: ...n in figure 18 4 Figure 18 5 shows the I 2 C bus timing The symbols used in figures 18 3 to 18 5 are explained in table 18 8 S A SLA 7 n R W DATA A 1 1 m 1 1 1 A A 1 P 1 Transfer bit count n 1 to 8 Tr...

Page 666: ...s the direction of data transfer from the slave device to the master device when R W is 1 or from the master device to the slave device when R W is 0 A Acknowledge The receiving device drives SDA low...

Page 667: ...ommunication format wait insertion and transfer rate MLS WAIT CKS2 to CKS0 Enable interrupt STOPIM HNDS ALIE ALSL FNC1 and FNC0 Set acknowledge bit ACKB Set ICMR Set ICCR Set IICE 1 in STCR Set SAR an...

Page 668: ...d and subsequent bytes After writing to ICDR clear IRIC immediately 2 Test the status of the SCL and SDA lines 7 Wait for 1 byte to be transmitted 10 Wait for 1 byte to be transmitted 11 Determine end...

Page 669: ...k and the data written to ICDR The selected slave device i e the slave device with the matching slave address drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal 7 When on...

Page 670: ...slave output 2 1 R W 4 3 6 5 8 7 1 2 9 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 ICDRE IRTR ICDRT Note Do not set ICDR during this period SCL master output Start condition generati...

Page 671: ...nce IRIC A 10 7 Data 1 Data 1 Data 2 User processing Figure 18 9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode MLS WAIT 0 18 4 4 Master Receive Operation In I 2 C bus format...

Page 672: ...t receiving The first read is a dummy read 5 Read the receive data for the second and subsequent read 3 Wait for 1 byte to be received Set IRIC at the rise of the 9th clock for the receive frame 6 Set...

Page 673: ...om ICDRS at the rise of the 9th clock pulse setting the ICDRF IRIC and IRTR flags to 1 If the IEIC bit has been set to 1 an interrupt request is sent to the CPU The master device drives SCL low from t...

Page 674: ...DR read Data 1 Undefined value Figure 18 11 Master Receive Mode Operation Timing Example MLS WAIT 0 HNDS 1 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 9 7 8 A A Bit 7 Bit 1 Bit 6 Bit 5 Bit 4...

Page 675: ...he rise of the 9th clock 12 Wait for a receive wait Set IRIC at the fall of the 8th clock or Wait for 1 byte to be received Set IRIC at the rise of the 9th clock 5 Read the receive data 6 Clear IRIC t...

Page 676: ...rtion 12 Wait for 1 byte to be received Set IRIC at the rise of the 9th clock 9 Set TRS for stop condition issuance 7 Set acknowledge data for the last reception 16 Read the last receive data Master r...

Page 677: ...are set to 1 indicating that one frame of data has been received The master device outputs the receive clock continuously to receive the next data 4 Read the IRTR flag in ICSR If the IRTR flag is 0 ex...

Page 678: ...clear the IRIC flag to 0 to release the wait state If the IRTR flag is 1 and data reception is complete execute step 15 to issue the stop condition 14 If IRTR flag is 0 clear the IRIC flag to 0 to re...

Page 679: ...IRTR 1 Figure 18 15 Master Receive Mode Operation Timing Example MLS ACKB 0 WAIT 1 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 9 8 A A Bit 7 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IRIC IR...

Page 680: ...t slave receive mode the master device outputs the transmit clock and transmit data and the slave device returns an acknowledge signal The slave device operates as the device specified by the master d...

Page 681: ...s Read IRIC in ICCR Set ACKB 1 in ICSR IRIC 1 No No Yes Yes TRS 1 IRIC 1 Yes Yes No Yes No AAS 1 and ADZ 1 1 Initialization Select slave receive mode 2 Read the receive data remaining unread 3 to 7 Wa...

Page 682: ...1 the TRS bit is set to 1 and slave transmit operation is performed When the slave address does not match receive operation is halted until the next start condition is detected 5 At the 9th clock pul...

Page 683: ...xed low until ICDR is read 2 ICDR read Interrupt request occurrence Figure 18 18 Slave Receive Mode Operation Timing Example 1 MLS 0 HNDS 1 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 8 9 Bit...

Page 684: ...C 1 ICDRF 1 Yes Yes No No Yes No AAS 1 and ADZ 1 No No 1 Select slave receive mode 2 Read the receive data remaining unread 3 to 7 Wait for one byte to be received slave address R W Set IRIC at the ri...

Page 685: ...e operation is halted until the next start condition is detected 5 At the 9th clock pulse of the receive frame the slave device returns the data in the ACKB bit as the acknowledge data 6 At the rise o...

Page 686: ...ead ICDR 15 Clear the IRIC flag SDA master output SDA slave output 2 1 4 3 2 1 4 3 6 5 8 7 9 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICDRF ICDRS ICDRR IRIC SCL master o...

Page 687: ...Bit 1 Bit 0 ICDRF ICDRS ICDRR IRIC SCL master output 9 Set ACKB 1 13 IRIC clear 10 ICDR read Data n 2 10 ICDR read Data n 1 13 IRIC clear 9 Wait for one frame User processing Bit 7 Bit 0 Bit 6 Bit 5...

Page 688: ...to 0 in ICCR ACKB 0 clear Clear IRIC in ICCR Read IRIC in ICCR Read ACKB in ICSR Set TRS 0 in ICCR Read ICDR Read IRIC in ICCR IRIC 1 Yes Yes No No IRIC 1 Yes No 1 2 If the slave address matches to t...

Page 689: ...The IRIC flag is cleared to 0 to detect the end of transmission Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously Prevent any other interrupt proces...

Page 690: ...OPIM bit in ICXR is 0 the IRIC flag is set to 1 If the IRIC flag has been set it is cleared to 0 SDA master output SDA slave output 2 1 2 1 4 3 6 5 8 7 9 9 8 Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 4 Bit 3...

Page 691: ...transferred this timing is synchronized with the internal clock Figures 18 25 to 18 27 show the IRIC set timing and SCL control SCL SDA IRIC User processing Clear IRIC 2 3 1 A 8 7 3 2 1 9 8 7 When WAI...

Page 692: ...WAIT 1 and FS 0 or FSX 0 I2C bus format wait inserted SCL SDA IRIC User processing Clear IRIC Write to ICDR transmit or read from ICDR receive 1 A 8 1 9 8 Clear IRIC a Data transfer ends with ICDRE 0...

Page 693: ...d FSX 1 clocked synchronous serial format a Data transfer ends with ICDRE 0 at transmission or ICDRF 0 at reception SCL SDA IRIC User processing Clear IRIC Clear IRIC Write to ICDR transmit or read fr...

Page 694: ...to 0 Therefore no interrupt is generated during continuous data transfer however if data transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1 DTC is not initiated thus...

Page 695: ...DTC ICDR read Transmission by DTC ICDR write Reception by DTC ICDR read Dummy data H FF write Processing by DTC ICDR write Last frame processing Not necessary Reception by CPU ICDR read Not necessary...

Page 696: ...the previous value is held System clock cycle Sampling clock C D Q Latch C D Q Latch SCL or SDA input signal Match detector Internal SCL or SDA signal Sampling clock Figure 18 28 Block Diagram of Nois...

Page 697: ...transmitting receiving at that point and the SCL and SDA pins will be released When transmission reception is started again register initialization etc must be carried out as necessary to enable corre...

Page 698: ...r independently Table 18 10 IIC Interrupt Source Channel Bit Name Enable Bit Interrupt Source Interrupt Flag DTC Activation Priority 2 IICI2 IEIC I 2 C bus interface interrupt request IRIC Possible Hi...

Page 699: ...and TRS 1 including automatic transfer from ICDRT to ICDRS Read from ICDR when ICE 1 and TRS 0 including automatic transfer from ICDRS to ICDRR 3 Table 18 11 shows the timing of SCL and SDA outputs i...

Page 700: ...on If tsr the time for SCL to go from low to VIH exceeds the time determined by the input clock of the I2 C bus interface the high period of SCL is extended The SCL rise time is determined by the pull...

Page 701: ...s interface specifications at any frequency The solution is either a to provide coding to secure the necessary interval approximately 1 s between issuance of a stop condition and issuance of a start c...

Page 702: ...0 4000 4100 3560 3765 0 5 tSCLO 2 tcyc tSr High speed mode 300 600 1000 900 935 Standard mode 1000 250 3600 3110 3368 tSDASO master 1 tSCLLO 3 3 tcyc tSr High speed mode 300 100 500 450 538 Standard m...

Page 703: ...ond byte of data If it is necessary to read the second byte of data issue the stop condition in master receive mode i e with the TRS bit cleared to 0 When reading the receive data first confirm that t...

Page 704: ...led period Bit 0 A 8 9 Stop condition a Start condition Execution of instruction for issuing stop condition write 0 to BBSY and SCP Confirmation of stop condition issuance read BBSY 0 Start condition...

Page 705: ...termination 5 ICDR write transmit data 2 Determination of SCL Low 1 IRIC determination Start condition generation retransmission IRIC 1 Yes Clear IRIC in ICCR Read SCL pin Write transmit data to ICDR...

Page 706: ...ance SDA 9th clock Secures a high period SCL is detected as low because the rise of the waveform is delayed Figure 18 31 Stop Condition Issuance Timing Note This restriction on usage can be canceled b...

Page 707: ...shaded in figure 18 33 However such read and write operations source no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse becaus...

Page 708: ...fore detecting the next rising edge on the SCL pin the time indicated as a in figure 18 34 the bit value becomes valid immediately when it is set However if the TRS bit is set during the other time th...

Page 709: ...ode Note This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B 11 in ICXR 13 Note on ICDR read in transmit mode and ICDR write in receive mode When ICDR is read in transmit...

Page 710: ...CKB bit to 0 Set receive mode TRS 0 before the next start condition is input in slave mode Complete transmit operation by the procedure shown in figure 18 23 in order to switch from slave transmit mod...

Page 711: ...the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode When the MST bit is set to 1 during data transmission or reception i...

Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...

Page 713: ...down functions that can control the PCI clock and shut down the LPC interface 19 1 Features Supports LPC interface I O read and I O write cycles Uses four signal lines LAD3 to LAD0 to transfer the cyc...

Page 714: ...SCIF SMI and HIRQ1 to HIRQ15 can be generated Operation can be switched between quiet mode and continuous mode The CLKRUN signal can be manipulated to restart the PCI clock LCLK Power down modes and...

Page 715: ...rial conversion Control logic Internal interrupt control Legend HICR0 to HICR5 LADR12H LADR12L LADR3H LADR3L IDR1 to IDR3 ODR1 to ODR3 STR1 to STR3 TWR1 to TWR15 TWR1 to TWR15 LAD0 to LAD3 HICR0 to HI...

Page 716: ...terrupt request SERIRQ PE7 I O 1 Serialized host interrupt request signal SMI HIRQ1 to HIRQ15 in synchronization with LCLK LSCI general output LSCI PD0 Output 1 2 General output LSMI general output LS...

Page 717: ...register H L LADR12H LADR12L LPC channel 3 address register H L LADR3H LADR3L Input data register 1 IDR1 Input data register 2 IDR2 Input data register 3 IDR3 Output data register 1 ODR1 Output data r...

Page 718: ...egister SMICDTR SMIC interrupt register 0 SMICIR0 SMIC interrupt register 1 SMICIR1 The following registers are necessary for BT mode BT status register 0 BTSR0 BT status register 1 BTSR1 BT control s...

Page 719: ...C Enable 3 to 1 Enable or disable the LPC interface function When the LPC interface is enabled one of the three bits is set to 1 processing for data transfer between the slave this LSI and the host is...

Page 720: ...tput is initialized to 1 1 Fast Gate A20 function enabled GA20 pin output is open drain external pull up resistor Vcc required 3 SDWNE 0 R W LPC Software Shutdown Enable Controls LPC interface shutdow...

Page 721: ...utput disabled general I O function of pin PD2 is enabled 1 0 PME output enabled PME pin output goes to 0 level 1 1 PME output enabled PME pin output is high impedance 1 LSMIE 0 R W LSMI output Enable...

Page 722: ...n combination with the LSCIB bit in HICR1 LSCI pin output is open drain and an external pull up resistor Vcc is needed The PD0DDR bit should be cleared to 0 when the LPC is used LSCIE LSCIB 0 X LSCI o...

Page 723: ...state Bus idle or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle Clearing conditions LPC hardware reset or LPC software reset LPC ha...

Page 724: ...is set to continuous mode There are no further interrupts for transfer to the host in quiet mode 1 LCLK restart request issued Setting condition In quiet mode SERIRQ interrupt output becomes necessary...

Page 725: ...C Software Shutdown Bit Controls LPC interface shutdown For details of the LPC shutdown function and the scope of initialization by an LPC reset and an LPC shutdown see section 19 4 6 LPC Interface Sh...

Page 726: ...e Slave Host Description 1 LSMIB 0 R W LSMI Output Bit Controls LSMI output in combination with the LSMIE bit For details refer to description on the LSMIE bit in HICR0 0 LSCIB 0 R W LSCI output Bit C...

Page 727: ...of the functions that use pin multiplexing HICR2 R W Bit Bit Name Initial Value Slave Host Description 7 GA20 Undefined R GA20 Pin Monitor 6 LRST 0 R W LPC Reset Interrupt Flag This bit is a flag tha...

Page 728: ...E 1 and LPCPD pin falling edge detection LPC software shutdown SDWNB 1 1 Setting condition LFRAME pin falling edge detection during LPC transfer cycle 3 IBFIE3 0 R W IDR3 and TWR Receive Complete inte...

Page 729: ...egister IDR1 receive complete interrupt requests disabled 1 Input data register IDR1 receive complete interrupt requests enabled 0 ERRIE 0 R W Error Interrupt Enable Enables or disables ERRI interrupt...

Page 730: ...d 1 LADR2 is selected 6 to 4 All 0 R W Reserved The initial value should not be changed 3 SWENBL 0 R W In BT mode H 5 short wait or H 6 long wait is returned to the host in the synchronized return cyc...

Page 731: ...in channel 3 When the LPC3E bit in HICR0 is 0 this bit is valid 0 BT interface operation is disabled No address LADR3 matches for BTIMSR BTCR or BTDTR 1 BT interface operation is enabled 19 3 4 Host I...

Page 732: ...isters LADR1H LADR1L LADR2H and LADR2L When the LADR12SEL bit in HICR4 is 0 LPC channel 1 host addresses LADR1H LADR1L are set through LADR12 The contents of the address field in LADR1 must not be cha...

Page 733: ...LADR1 bits 15 to 3 1 LADR1 bit 1 LADR1 bit 0 I O read STR1 read LADR2 bits 15 to 3 0 LADR2 bit 1 LADR2 bit 0 I O write IDR2 write data C D2 0 LADR2 bits 15 to 3 1 LADR2 bit 1 LADR2 bit 0 I O write IDR...

Page 734: ...Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 All 0 R W Channel 3 Address Bits 15 to 8 The host address of LPC channel 3 is set LADR3L R W Bit Bit Name Initial Value Slave Host Description 7...

Page 735: ...DTR BTCR BTIMSR address match in BT mode the values of bits 3 to 0 are ignored Register selection according to the bits ignored in address match determination is as shown in the following table I O Ad...

Page 736: ...on Bits 15 to5 Bit 4 0 1 0 0 I O write BTCR write Bits 15 to5 Bit 4 0 1 0 1 I O write BTDTR write Bits 15 to5 Bit 4 0 1 1 0 I O write BTIMSR write Bits 15 to5 Bit 4 0 1 0 0 I O read BTCR read Bits 15...

Page 737: ...d register The state of bit 2 of the I O address is latched into the C D bit in STR to indicate whether the written information is a command or data The initial values of the IDR registers are undefin...

Page 738: ...while TWR0SW is a write only register to the slave processor and a read only register to the host processor When the host and slave processors begin a write after the respective TWR0 registers have b...

Page 739: ...lowing sections For information on STR1 and STR2 selection see section 19 3 6 LPC Channel 1 2 Address Register H L LADR12H LADR12L and information on STR3 selection see section 19 3 7 LPC Channel 3 Ad...

Page 740: ...ee table 19 7 0 There is not receive data in IDR1 Clearing condition When the slave processor reads IDR 1 There is receive data in IDR1 Setting condition When the host processor writes to IDR using I...

Page 741: ...H2OFFSEL1 1 is written to this bit to indicate whether IDR2 contains data or a command 0 Content of input data register IDR2 is a data 1 Content of input data register IDR2 is a command 2 DBU22 0 R W...

Page 742: ...R Output Data Register Full Indicates whether or not there is transmit data in ODR2 0 There is not transmit data in ODR2 Clearing conditions When the host reads ODR2 in an I O read cycle When the sla...

Page 743: ...Output Buffer Full Flag 0 Clearing conditions When the host reads TWR15 in I O read cycle When the slave writes 0 to the OBF3B bit 1 Setting condition When the slave writes to TWR15 5 MWMF 0 R R Maste...

Page 744: ...nput Data Register Full Indicates whether or not there is receive data in IDR3 This is an internal interrupt source to the slave this LSI 0 There is not receive data in IDR3 Clearing condition When th...

Page 745: ...en into this bit to indicate whether IDR3 contains data or a command 0 Content of input data register IDR3 is a data 1 Content of input data register IDR3 is a command 2 DBU32 0 R W R Defined by User...

Page 746: ...W R Output Data Register Full Indicates whether or not there is transmit data in ODR3 0 There is not receive data in ODR3 Clearing conditions When the host reads ODR3 in an I O read cycle When the sla...

Page 747: ...pecification by SERIRQ transfer cycle stop frame 6 SELREQ 0 R W Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrupt request is cleared...

Page 748: ...1 When IEDIR3 0 Host SMI interrupt request by setting OBF3B to 1 is enabled When IEDIR3 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE3B 0 3 SMIE3A 0 R W Host SMI In...

Page 749: ...aring OBF2 to 0 when IEDIR2 0 1 When IEDIR2 0 Host SMI interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE2 0...

Page 750: ...terrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write 0 HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled Clearing conditions Writing 0 to IRQ1E1 L...

Page 751: ...Q11E3 LPC hardware reset LPC software reset Clearing OBF3A to 0 when IEDIR3 0 1 When IEDIR3 0 HIRQ11 interrupt request by setting OBF3A to 1 is enabled When IEDIR3 1 HIRQ11 interrupt is requested Sett...

Page 752: ...0 1 When IEDIR3 0 HIRQ9 interrupt request by setting OBF3A to 1 is enabled When IEDIR3 1 HIRQ9 interrupt is requested Setting condition Writing 1 after reading IRQ9E3 0 4 IRQ6E3 0 R W Host IRQ6 Interr...

Page 753: ...1 When IEDIR2 0 HIRQ11 interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 HIRQ11 interrupt is requested Setting condition Writing 1 after reading IRQ11E2 0 2 IRQ10E2 0 R W Host IRQ10 Inte...

Page 754: ...0 1 When IEDIR2 0 HIRQ9 interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 HIRQ9 interrupt is requested Setting condition Writing 1 after reading IRQ9E2 0 0 IRQ6E2 0 R W Host IRQ6 Interr...

Page 755: ...itial Value Slave Host Description 7 IEDIR3 0 R W Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by a...

Page 756: ...iption 7 to 4 All 0 R W Reserved The initial value should not be changed 3 2 1 0 SCSIRQ3 SCSIRQ2 SCSIRQ1 SCSIRQ0 0 0 0 0 R W R W R W R W SCIF SERIRQ Interrupt Select These bits select the SCIF interru...

Page 757: ...IRQ13 Interrupt Enable 0 Disables HIRQ13 interrupt request by IRQ13E 1 Enables HIRQ13 interrupt request 4 IRQ8E 0 R W Host IRQ8 Interrupt Enable 0 Disables HIRQ8 interrupt request by IRQ8E 1 Enables H...

Page 758: ...7 SELIRQ5 SELIRQ4 SELIRQ3 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W SERIRQ Output Select These bits select the state of the output on the pin for LPC host interrupt requests HIRQ15 HIRQ14 HIRQ13...

Page 759: ...ts 7 to 4 in STR3 indicate processing status of the LPC interface 1 When TWRE 1 Bits 7 to 4 in STR3 indicate processing status of the LPC interface When TWRE 0 Bits 7 to 4 in STR3 are readable writabl...

Page 760: ...it Name Initial Value Slave Host Description 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 1 R W 0 1 R W SCIF Address 15 to 8 These bits set the host address for the SCIF SCIFADRL R W Bit Bit Name...

Page 761: ...eady for the host read transfer 6 TX_DATA_RDY 0 R W R Write Transfer Ready Indicates whether or not the slave is ready for the host next write transfer 0 The slave waits for ready status 1 The slave i...

Page 762: ...0 can be written to clear the flag 19 3 21 SMIC Control Status Register SMICCSR SMICCSR is one of the registers used to implement SMIC mode This is an 8 bit readable writable register that stores a c...

Page 763: ...set to 1 the IBFI3 interrupt is requested to the slave 0 Transfer data transmission wait state Clearing condition After the slave reads HDTWI 1 writes 0 to this bit 1 Transfer data transmission end Se...

Page 764: ...a status flag that indicates that the host has finished transmitting the control code to SMICCSR When the IBFIE3 bit and CTLWIE bit are set to1 the IBFI3 interrupt is requested to the slave 0 Control...

Page 765: ...pt 3 HDTRIE 0 R W Transfer Data Receive End Interrupt Enable Enables or disables HDTRI interrupt that is IBFI3 interrupt source to the slave 0 Disables transfer data receive end interrupt 1 Enables tr...

Page 766: ...DIE bit are set to 1 IBFI3 interrupt is requested to the slave The slave must clear the flag after creating an unused area by reading the data in FIFO 0 FIFO read is not requested Clearing condition A...

Page 767: ...ng condition After the slave reads HWRI 1 writes 0 to this bit 1 The host writes to BTDTR Setting condition The host writes one byte to BTDTR 1 HBTWI 0 R W BTDTR Host Write Start Interrupt This status...

Page 768: ...ndicates that the host reads all valid data from BTDTR buffer When the BFIE3 bit and HBTRIE bit are set to 1 IBFI3 interrupt is requested to the slave 0 BTDTR host read end wait state Clearing conditi...

Page 769: ..._HWRST bit in BTIMSR is set to 1 by the host When the IBFIE3 bit and HRSTIE bit are set to 1 IBFI3 interrupt is requested to the slave 0 Clearing condition When the slave reads HRSTI 1 and writes 0 to...

Page 770: ...ad End Interrupt This status flag indicates that the host has finished reading all data from the BTDTR buffer When the IBFIE3 bit and B2HIE bit are set to 1 the IBFI3 interrupt is requested to the sla...

Page 771: ...0 Clearing condition After the slave reads CRRPI 1 writes 0 to this bit 1 Setting condition When the slave detects the rising edge of CLR_RD_PTR 0 CRWPI 0 R W Write Pointer Clear Interrupt This statu...

Page 772: ...ed The FIFO size 64 bytes for host write transfer additional 64 bytes for host read transfer 4 FRDIE 0 R W FIFO Read Request Interrupt Enable Enables or disables the FRDI interrupt which is an IBFI3 i...

Page 773: ...upt is enabled Note X Don t care 19 3 28 BT Control Status Register 1 BTCSR1 BTCSR1 is one of the registers used to implement the BT mode The BTCSR1 register contains the bits used to enable or disabl...

Page 774: ...Enables or disables the B2HI interrupt which is an IBFI3 interrupt source to the slave 0 Read end interrupt is disabled 1 Read end interrupt is enabled 2 H2BIE 0 R W Write End Interrupt Enable Enable...

Page 775: ...1 Indicates that the BTDTR buffer is being used 6 H_BUSY 0 R W 3 BT Read Transfer Busy Flag This is a set clear bit from the host Indicates that the BTDTR buffer is being used for BT read transfer re...

Page 776: ...ication Flag This status flag indicates that the slave has finished writing all data to the BTDTR buffer Setting the B2H_IRQ_EN bit in the BTIMSR register enables the B2H_ATN bit to be used as an inte...

Page 777: ...pointer clear Setting condition When the host writes a 1 0 CLR_WR_ PTR 0 R W 2 W 1 Write Pointer Clear This bit is used by the host to clear the write pointer during write transfer A host read operati...

Page 778: ...stored in FIFO 64 bytes for host read transfer and read out by the host in order of slave writing 19 3 31 BT Interrupt Mask Register BTIMSR BTIMSR is one of the registers used to implement BT mode Th...

Page 779: ...e BEVT_ATN or B2H_ATN bit has been set The SERIRQ is not issued To generate the SERIRQ it should be issued by the program 0 B2H_IRQ interrupt is not requested Clearing condition When the host writes a...

Page 780: ...es that have been written to Further when data is read from the slave the value is decremented by only the number of bytes that have been read 19 3 33 BT FIFO Valid Size Register 1 BTFVSR1 BTFVSR1 is...

Page 781: ...and LADR2 to determine the I O address 3 When using channel 3 set LADR3 to determine the I O address and whether bidirectional data registers are to be used 4 When using the SCIF module set SCIFAR to...

Page 782: ...nges are made at this timing so in the event of a transfer cycle forced termination abort registers and flags are not changed The timing of the LFRAME LCLK and LAD signals is shown in figures 19 2 and...

Page 783: ...ction and size 1 1 4 1 2 2 2 1 Figure 19 2 Typical LFRAME Timing ADDR Start LFRAME LAD3 to LAD0 LCLK TAR Sync Cycle type direction and size Slave must stop driving Too many Syncs cause timeout Master...

Page 784: ...G to indicate transfer completion Slave confirms that status code is read from SMICCSR by host The STARI bit in SMICIR0 is set Slave confirms that valid data is written to SMICDTR by host The HDTWI bi...

Page 785: ...n Slave confirms that status code is read from SMICCSR by host The STARI bit in SMICIR0 is set Slave confirms that valid data is read from SMICDTR by host The HDTRI bit in SMICIR0 is set Slave confirm...

Page 786: ...B_ATN bit in BTCR to indicate data write completion to the buffer for the BT interface Clear write pointer B_BUSY 1 Generate slave interrupt Generate slave interrupt Generate slave interrupt Slave wai...

Page 787: ...setting the CLR_RD_PTR bit in BTCR H_BUSY 1 Generate slave interrupt Generate host interrupt Generate slave interrupt Generate slave interrupt Host waits for the B2H_ATN bit interrupt from slave is s...

Page 788: ...o 1 since the initial value of the FGA20E bit is 0 When the FGA20E bit is set to 1 pin P81 GA20 functions as the output of the fast GA20 signal The state of pin GA20 can be monitored by reading bit GA...

Page 789: ...LPC Rev 1 00 Mar 12 2008 Page 741 of 1178 REJ09B0403 0100 Start Wait for next byte H D1 command received Host write Host write Yes No Data byte No Write bit 1 of data byte to the bit of GA20 in DR Yes...

Page 790: ...f sequence 1 H D1 command 0 Q 0 1 data 1 0 1 1 0 Command other than H FF and H D1 1 Q 1 Turn on sequence abbreviated form 1 H D1 command 0 Q 0 0 data 2 0 0 1 0 Command other than H FF and H D1 1 Q 0 T...

Page 791: ...tware shutdown state is set by means of the SDWNB bit on the other hand the LPC software shutdown state cannot be cleared at the same time as the rising edge of the LPCPD signal Taking these points in...

Page 792: ...t Needed to clear shutdown state Legend O Pin that is shutdown by the shutdown function Pin that is shutdown only when the LPC function is selected by register setting X Pin that is not shutdown In th...

Page 793: ...flag Initialized 0 Can be set cleared Can be set cleared SDWN flag Initialized 0 Initialized 0 Can be set cleared LRSTB bit Initialized 0 HR 0 SR 1 0 can be set SDWNB bit Initialized 0 Initialized 0 H...

Page 794: ...0 Mar 12 2008 Page 746 of 1178 REJ09B0403 0100 Figure 19 9 shows the timing of the LPCPD and LRESET signals LPCPD LRESET LAD3 to LAD0 LFRAME LCLK At least 30 s At least 100 s At least 60 s Figure 19 9...

Page 795: ...host or a peripheral function and a request signal is generated by the frame corresponding to that interrupt The timing is shown in figure 19 10 IRQ1 IRQ1 Host controller None None SERIRQ Drive source...

Page 796: ...possible in LPC channel 1 and SCIF 3 SMI Slave 3 Drive possible in LPC channels 2 3 and SCIF 4 IRQ3 Slave 3 Drive possible in SCIF or by IRQ3E 5 IRQ4 Slave 3 Drive possible in SCIF or by IRQ4E 6 IRQ5...

Page 797: ...erface Clock Start Request A request to restart the clock LCLK can be sent to the host by means of the CLKRUN pin With LPC data transfer and SERIRQ in continuous mode a clock restart is never requeste...

Page 798: ...I interrupt indicates the occurrence of a special state such as an LPC reset LPC shutdown or transfer cycle abort The LMCI and LMCUI interrupts are command receive complete interrupts Table 19 11 Rece...

Page 799: ...sponding LPC channel the corresponding host interrupt enable bit is automatically cleared to 0 and the host interrupt request is cleared When the IEDIR bit is set to 1 in SIRQCR a host interrupt is on...

Page 800: ...0 from bit SMIE3B and writes 1 Internal CPU writes 0 to bit SMIE2 or host reads ODR2 writes 0 to bit SMIE3A or host reads ODR3 writes 0 to bit SMIE3B or host reads TWR15 SMI IEDIR2 1 or IEDIR3 1 Inte...

Page 801: ...tion SMI HIRQi i 1 3 to 15 The SCIF interrupt corresponding to the host interrupt request selected by SIRQCR3 occurs Relevant SCIF interrupt is cleared Slave CPU Master CPU ODR1 write Write 1 to IRQ1E...

Page 802: ...DR at the same time the data will be corrupted To prevent simultaneous accesses IBF and OBF must be used to allow access only to data for which writing has finished Unlike the IDR and ODR registers th...

Page 803: ...and H A24E H 3FD0 and H 3FD4 ODR3 H A24A H 3FD0 STR3 H A24E H 3FD4 TWR0MW H A250 H 3FC0 TWR0SW H A250 H 3FC0 TWR1 H A251 H 3FC1 TWR2 H A252 H 3FC2 TWR3 H A253 H 3FC3 TWR4 H A254 H 3FC4 TWR5 H A255 H 3...

Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...

Page 805: ...This LSI has one MAC layer interface The Ethernet controller is connected to the direct memory access controller for Ethernet controller E DMAC inside this LSI and carries out high speed data transfer...

Page 806: ...therC Rev 1 00 Mar 12 2008 Page 758 of 1178 REJ09B0403 0100 Bus interface Transmit controller Receive controller Command status interface Converter MII RMII conversion CPU EtherC MAC PORT PHY MII Figu...

Page 807: ...data RM_CRS DV Input Carrier Detection Receive Data Valid Carrier detection signal Signal that indicates that valid receive data is on pins RM_RXD1 and RM_RXD0 RM_RXD1 RM_RXD0 Input Receive Data 2 bit...

Page 808: ...ster MALR Receive frame length register RFLR PHY status register PSR Transmit retry over counter register TROCR Delayed collision detect counter register CDCR Lost carrier counter register LCCR Carrie...

Page 809: ...SE Frame Use Enable 0 Disables PAUSE frame control in which the TIME parameter is 0 The next frame is transmitted after the time indicated by the Timer value has elapsed When the EtherC receives a PAU...

Page 810: ...remented If this bit is clear and a frame with an error is received a CRC error is reflected in ECSR of the E DMAC and the status of the receive descriptor If this bit is set to 1 a frame with an erro...

Page 811: ...ransmission reception is performed 1 When DM 1 data loopback is performed inside the MAC in the EtherC 2 0 R Reserved This bit is always read as 0 The initial value should not be changed 1 DM 0 R W Du...

Page 812: ...ays read as 0 The initial value should not be changed 4 PSRTO 0 R W PAUSE Frame Retransmission Retry Over Indicates that during the retransmission of PAUSE frames when the flow control is enabled the...

Page 813: ...s not been detected 1 Magic Packet has been detected 0 ICD 0 R W Illegal Carrier Detection Indicates that the PHY has detected an illegal carrier on the line If a change in the signal input from the P...

Page 814: ...smission Retry Over Interrupt Enable 0 Interrupt notification by the PSRTO bit is disabled 1 Interrupt notification by the PSRTO bit is enabled 3 0 R Reserved This bit is always read as 0 The initial...

Page 815: ...3 MDI Undefined R MII Management Data In Indicates the level of the MDIO pin 2 MDO 0 R W MII Management Data Out Outputs the value set to this bit from the MDIO pin when the MMD bit is 1 1 MMD 0 R W...

Page 816: ...the MAC address is 01 23 45 67 89 AB hexadecimal the value set in this register is H 01234567 20 3 6 MAC Address Low Register MALR MALR is a 32 bit readable writable register that specifies the lower...

Page 817: ...se bits are always read as 0 The initial value should not be changed 11 to 0 RFL11 to RFL0 All 0 R W Receive Frame Length 11 to 0 The frame length described here refers to all fields from the destinat...

Page 818: ...e PHY specifications to be connected 20 3 9 Transmit Retry Over Counter Register TROCR TROCR is a 32 bit counter that indicates the number of frames that were unable to be transmitted in 16 transmissi...

Page 819: ...es the number of times the carrier was lost during data transmission When the value in this register reaches H FFFFFFFF the count is halted The counter value is cleared to 0 by writing to this registe...

Page 820: ...ndicated by the RM_RX ER pin FRECR is incremented each time the RM_RX ER pin becomes active When the value in this register reaches H FFFFFFFF the count is halted The counter value is cleared to 0 by...

Page 821: ...th exceeding the value in RFLR 20 3 17 Residual Bit Frame Counter Register RFCR RFCR is a 32 bit counter that indicates the number of frames received containing residual bits less than an 8 bit unit W...

Page 822: ...to 0 IPG4 to IPG0 H 13 R W Inter Packet Gap Sets the IPG value every 4 bit time H 00 20 bit time H 01 24 bit time H 13 96 bit time Initial value H 1F 144 bit time 20 3 20 Automatic PAUSE Frame Set Re...

Page 823: ...TIME parameter value of the manual PAUSE frame At this time 1 bit means 512 bit time Read values are undefined 20 3 22 Automatic PAUSE Frame Retransmission Count Set Register TPAUSER TPAUSER sets the...

Page 824: ...mits and receives PAUSE frames conforming to the Ethernet IEEE802 3 frames 20 4 1 Transmission In response to a transmit request from the E DMAC the EtherC transmitter arranges the transmit data into...

Page 825: ...sion is detected during transmission of data greater than 512 bits only jam is transmitted and retransmission based on the back off algorithm is not performed Error notification Transmission halted St...

Page 826: ...val time If full duplex transfer is selected which does not require carrier detection the preamble is sent as soon as a transmit request is issued by the E DMAC 3 The transmitter sends the SFD data an...

Page 827: ...Note The error frame also transmits data to the buffer End of reception Receive error detection Receive error detection Error detection Promiscuous and other station destination address RE reset Norm...

Page 828: ...receive the next frame 20 4 3 RMII Frame Timing 1 RMII Frame Transmission Timing Timing of RMII frame transmission is shown in figure 20 4 RM_TXD1 RM_TXD0 RM_REF CLK RM_TX EN Preamble SFD Data 0 0 0...

Page 829: ...r 12 2008 Page 781 of 1178 REJ09B0403 0100 RM_RXD1 RM_RXD0 RM_REF CLK RM_CRS DV False Carrier detected 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 6 RMII...

Page 830: ...RR RRRRR TA 2 Z0 10 DATA 16 D D D D IDLE X PRE ST OP PHYAD REGAD TA DATA IDLE Legend 32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the P...

Page 831: ...w examples of MII register access timing The timing will differ depending on the type of PHY LSI MDC MDO 1 2 3 1 2 3 Write to PHY interface register MMD 1 MDO write data MDC 0 MMD 1 MDO write data MDC...

Page 832: ...HY interface register MMD 0 MDC 1 3 Write to PHY interface register MMD 0 MDC 0 2 Read from PHY interface register read MMD 0 MMC 1 MDI is read data Figure 20 10 1 Bit Data Read Flowchart MDC MDO 1 1...

Page 833: ...DMAC mode register EDMR With a Magic Packet reception is performed regardless of the destination address As a result this function is valid and the WOL pin enabled only in the case of a match with the...

Page 834: ...conforming to IEEE802 3x in full duplex operations Flow control can be applied to both receive and transmit operations The methods for transmitting PAUSE frames when controlling flow are as follows 1...

Page 835: ...by directives from the software When writing the Timer value to the manual PAUSE frame set register MPR manual PAUSE frame transmission is started With this method PAUSE frame transmission is carried...

Page 836: ...received is incorrectly applied As a result unnecessary waiting time is generated to slow down the transmission throughput The TIME parameter value is maintained until another PAUSE frame is received...

Page 837: ...tation is not so high Therefore the transmission of PAUSE frames during this period is less likely to happen The possibility that this defect actually affects the operation in this LSI is rather low 2...

Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...

Page 839: ...E DMAC itself using descriptors This lightens the load on the CPU and enables efficient data transfer control to be achieved 21 1 Features The E DMAC has the following features The load on the CPU is...

Page 840: ...and Descriptors and Buffers 21 2 Register Descriptions The E DMAC has the following registers E DMAC mode register EDMR E DMAC transmit request register EDTRR E DMAC receive request register EDRRR Tr...

Page 841: ...iving method control register RMCR Receive buffer write address register RBWAR Receive descriptor fetch address register RDFAR Transmit buffer read address register TBRAR Transmit descriptor fetch add...

Page 842: ...register then make new settings It takes 64 states to initialize the EtherC and E DMAC Therefore registers of the EtherC and E DMAC should be accessed after 64 states have elapsed Bit Bit Name Initial...

Page 843: ...The EDTRR is a 32 bit readable writable register that issues transmit directives to the E DMAC When transmission of one frame is completed the next descriptor is read If the transmit descriptor activ...

Page 844: ...he receive DMAC is halted Bit Bit Name Initial value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 0 RR 0 R W Receive Request Check R...

Page 845: ...follows according to the specified descriptor length 16 byte boundary TDLA3 to TDLA0 0000 32 byte boundary TDLA4 to TDLA0 00000 64 byte boundary TDLA5 to TDLA0 000000 21 2 5 Receive Descriptor List Ad...

Page 846: ...rrupts generated by this register are EINT0 For interrupt priority see section 5 5 Interrupt Exception Handling Vector Table Bit Bit Name Initial value R W Description 31 0 R Reserved This bit is alwa...

Page 847: ...frame counter has not overflowed 1 Receive frame counter overflows 23 ADE 0 R W Address Error Indicates that the memory address that the E DMAC tried to transfer is found illegal 0 Illegal memory addr...

Page 848: ...descriptor 0 Transfer not complete or no transfer directive 1 Transfer complete 20 TDE 0 R W Transmit Descriptor Empty Indicates that the transmission descriptor valid bit TACT in the descriptor is n...

Page 849: ...riptor active bit RACT 0 detected 16 RFOF 0 R W Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception 0 Overflow has not occurred 1 Overflow has occurred 15 to 12...

Page 850: ...en received 6 5 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 4 RRF 0 R W Receive Residual Bit Frame 0 Residual bit frame has not been received 1 Residual bi...

Page 851: ...ays read as 0 The initial value should not be changed 26 TABTIP 0 R W Transmit Abort Detection Interrupt Permission 0 Transmit abort detection interrupt is disabled 1 Transmit abort detection interrup...

Page 852: ...led 1 Receive descriptor empty interrupt is enabled 16 RFOFIP 0 R W Receive FIFO Overflow Interrupt Permission 0 Receive FIFO overflow interrupt is disabled 1 Receive FIFO overflow interrupt is enable...

Page 853: ...Receive residual bit frame interrupt is disabled 1 Receive residual bit frame interrupt is enabled 3 RTLFIP 0 R W Receive Too Long Frame Interrupt Permission 0 Receive too long frame interrupt is disa...

Page 854: ...criptor After this LSI is reset all bits are cleared to 0 Bit Bit Name Initial value R W Description 31 to 12 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 1...

Page 855: ...the receive descriptor 3 RTLFCE 0 R W RTLF Bit Copy Directive 0 Indicates the RTLF bit state in bit RFS3 of the receive descriptor 1 Occurrence of the corresponding interrupt is not indicated in bit R...

Page 856: ...16 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 15 to 0 MFC15 to MFC0 All 0 R Missed Frame Counter Indicate the number of frames that are discarded and not...

Page 857: ...ng a transmit FIFO the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR The values between H 201 to H 7FF should not be set H 00 Store and forward modes H 01 to...

Page 858: ...itial value should not be changed 10 to 8 TFD2 to TFD0 B 000 R Transmit FIFO Capacity Specify the capacity of transmit FIFO from 256 bytes to 2048 bytes in 256 byte units The set value should not be c...

Page 859: ...ust be set during the receiving halt state Bit Bit Name Initial value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The initial value should not be changed 0 RNC 0 R W Recei...

Page 860: ...formation from the receiving descriptor Which receiving descriptor information is used for processing by the E DMAC can be recognized by monitoring addresses displayed in this register The address fro...

Page 861: ...t readable writable register that sets the flow control of the EtherC setting the threshold on automatic PAUSE transmission The threshold can be specified by the depth of the receive FIFO data RFD2 to...

Page 862: ...d in the receive FIFO 110 When 14 receive frames have been stored in the receive FIFO 111 When 16 receive frames have been stored in the receive FIFO 15 to 3 All 0 Reserved These bits are always read...

Page 863: ...it Receive Rate 0 10 Mbps 1 100 Mbps 21 2 19 Transmit Interrupt Register TRIMD TRIMD is a 32 bit readable writable register that specifies whether or not to notify write back completion for each frame...

Page 864: ...ecute transmission and reception continuously 21 3 1 Descriptor List and Data Buffers Before starting transmission reception the communication program creates transmit and receive descriptor lists in...

Page 865: ...817 of 1178 REJ09B0403 0100 Transmit descriptor Transmit buffer Valid transmit data T A C T T D L E T F P 1 T F P 0 TFS26 to TFS0 TD0 TDL TD1 TBA Padding 4 bytes TD2 31 30 29 28 27 26 0 T F E 31 16 31...

Page 866: ...ite back operation on termination of E DMAC frame transfer processing completion or suspension of transmission If this state is recognized in an E DMAC descriptor read the E DMAC terminates transmit p...

Page 867: ...indicated by this descriptor is start of frame frame is not concluded 11 Contents of transmit buffer indicated by this descriptor are equivalent to one frame one frame one buffer 27 TFE 0 R W Transmi...

Page 868: ...e length in the corresponding transmit buffer If set to 0 the operation is not guaranteed When the one frame multi buffer system is specified TFP1 and TF0 in TD0 B 10 or B 00 the transfer byte length...

Page 869: ...length Finally the actual receive frame length is reported in the lower 16 bits of RD1 in the descriptor Data transfer to the receive buffer is performed automatically by the E DMAC to give a one fram...

Page 870: ...ion of E DMAC frame transfer processing completion or suspension of reception If this state is recognized in an E DMAC descriptor read the E DMAC terminates receive processing and receive operations c...

Page 871: ...fer indicated by this descriptor contains end of frame frame is concluded 10 Receive buffer indicated by this descriptor is start of frame frame is not concluded 11 Contents of receive buffer indicate...

Page 872: ...FOF bit in EESR RFS8 Reserved The write value should always be 0 RFS7 Multicast address frame received corresponds to RMAF bit in EESR RFS6 CAM entry unregistered frame received corresponds to the RUA...

Page 873: ...ne frame per buffer is 1 514 bytes excluding the CRC data Therefore for the receive buffer length specification a value of 1 520 bytes H 05F0 that takes account of a 16 byte boundary is set as the max...

Page 874: ...smit buffer start address specified by TD2 and transfers it to the EtherC The EtherC creates a transmit frame and starts transmission to the MII After DMA transfer of data equivalent to the buffer len...

Page 875: ...ission flowchart E DMAC EtherC Ethernet Transmit FIFO EtherC E DMAC initialization Descriptor and transmit buffer setting Transmit directive Descriptor read Descriptor write back Descriptor write back...

Page 876: ...ers the frame to the receive buffer specified by RD2 If the data length of the received frame is greater than the buffer length given by RD1 the E DMAC performs write back to the descriptor when the b...

Page 877: ...MAC EtherC Receive FIFO Ethernet EtherC E DMAC initialization Descriptor and receive buffer setting Reception completed Receive data transfer Receive data transfer Frame reception Start of reception D...

Page 878: ...end B 01 In the case of a continuing descriptor the TACT bit is cleared to 0 only and the next descriptor is read immediately If the descriptor is the final descriptor not only is the TACT bit cleared...

Page 879: ...he first descriptor part where the RACT bit 1 in the figure reception is halted immediately and a status write back to the descriptor is performed If error interrupts are enabled in the EtherC E DMAC...

Page 880: ...Section 21 Ethernet Controller Direct Memory Access Controller E DMAC Rev 1 00 Mar 12 2008 Page 832 of 1178 REJ09B0403 0100...

Page 881: ...nd processing by firmware Transfer speed Supports full speed 12 Mbps Endpoint configuration Endpoint Name Abbreviation Transfer Type Maximum Packet Size FIFO Buffer Capacity Byte DTC Transfer Endpoint...

Page 882: ...ller Legend Figure 22 1 Block Diagram of USB 22 2 Input Output Pins Table 22 1 shows the USB pin configuration Table 22 1 Pin Configuration Pin Name I O Function VBUS Input USB cable connection monito...

Page 883: ...enable register 1 IER1 Interrupt enable register 2 IER2 EP0i data register EPDR0i EP0o data register EPDR0o EP0s data register EPDR0s EP1 data register EPDR1 EP2 data register EPDR2 EP3 data register...

Page 884: ...ue R W Description 7 BRST 0 R W Bus Reset This bit is set to 1 when a bus reset signal is detected on the USB bus 6 EP1FULL 0 R W EP1 FIFO Full Reading This bit is set when endpoint 1 receives one pac...

Page 885: ...bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side and returns an ACK handshake to the host 2 EP0oTS 0 R W EP0o Receive Complete This bit...

Page 886: ...nged 3 VBUS MN 0 R This is a status bit which monitors the state of the VBUS pin This bit reflects the state of the VBUS pin and generates no interrupt request This bit is always 0 when the PULLUP_E b...

Page 887: ...is a status bit that describes bus state 0 Normal state 1 Suspended state This bit is a status bit and generates no interrupt request 4 SURSF 0 R W Suspend Resume Detection This bit is set to 1 when...

Page 888: ...the interrupt corresponding to the bit will be USBINTN2 If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1 the corresponding interrupt will be USBINTN3 Bit Bit Name Ini...

Page 889: ...P3 Transfer Request 1 EP3 TS 1 R W EP3 Transmission Complete 0 VBUSF 1 R W USB Bus Connect 22 3 6 Interrupt Select Register 2 ISR2 ISR2 selects the vector numbers of the interrupt requests indicated i...

Page 890: ...0 R W EP2 FIFO Empty 3 SETUP TS 0 R W Setup Command Receive Complete 2 EP0o TS 0 R W EP0o Receive Complete 1 EP0i TR 0 R W EP0i Transfer Request 0 EP0i TS 0 R W EP0i Transmission Complete 22 3 8 Inter...

Page 891: ...ue should not be changed 4 SURSE 0 R W Suspend Resume Detection For the details of the operation see section 22 5 3 Suspend and Resume Operations 3 CFDN 0 R W End Point Information Load End 2 SOF 0 R...

Page 892: ...ata register for control out transfer 22 3 12 EP0s Data Register EPDR0s EPDR0s is an 8 byte FIFO buffer specifically for receiving endpoint 0 setup commands Only the setup command to be processed by t...

Page 893: ...2 EPDR2 has a dual buffer configuration and has a capacity of twice the maximum packet size When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set one packet of...

Page 894: ...ed side can be read by CPU Bit Bit Name Initial Value R W Description 7 to 0 All 0 R Number of received bytes for endpoint 1 22 3 18 Trigger Register TRG TRG generates one shot triggers to control the...

Page 895: ...r data for the EP0s command FIFO has been read Writing 1 to this bit enables transfer of data in the following data stage A NAK handshake is returned in response to transfer requests from the host in...

Page 896: ...st or when the FIFO clear bit for the corresponding endpoint in the FIFO clear register FCLR is set Bit Bit Name Initial Value R W Description 7 6 0 0 R R Reserved These bits are always read as 0 The...

Page 897: ...Value R W Description 7 Undefined Reserved The initial value should not be changed 6 EP3 CLR Undefined W EP3 Clear Writing 1 to this bit initializes the endpoint 3 transmit FIFO buffer 5 EP1 CLR Undef...

Page 898: ...med in byte units To initiate transfer by the DTC necessary settings must be made to the DTC in addition to the setting of this register Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reser...

Page 899: ...the other of the two FIFOs the DTC start interrupt signal USBINTN1 is asserted again However if the size of the data packet to be transmitted is less than 64 bytes the EP2 packet enable bit is not set...

Page 900: ...FIFO buffer the DTC start interrupt signal USBINTN0 is asserted In DTC transfer when all the received data is read EP1 is automatically read and the completion trigger operates EP1 related interrupt r...

Page 901: ...leared When the SETUPTS flag in the IFR0 register is set to 1 writing 1 to the EP0 STL bit is ignored For detailed operation see section 22 7 Stall Operations Bit Bit Name Initial Value R W Descriptio...

Page 902: ...in IFR2 is set to 1 3 0 R Reserved This bit is always read as 0 The initial value should not be changed 2 ALTV2 0 R 1 ALTV1 0 R 0 ALTV0 0 R These bits store Alternate Setting value when they receive S...

Page 903: ...not be changed 1 ASCE 0 R W Automatic Stall Clear Enable Setting the ASCE bit to 1 automatically clears the stall setting bit the EPxSTL x 1 2 or 3 bit in EPSTLR0 or EPSTR1 of the end point that has...

Page 904: ...a power on reset and no data should be written after that Description of writing data for one endpoint is shown below Although this register consists of one register to which data is written sequentia...

Page 905: ...prohibited 2 Bulk 3 Interrupt 3 D3 Undefined W Endpoint Transmission Direction Possible setting range 0 Out 1 In 2 to 0 D2 to D0 Undefined W Reserved Possible setting range Fixed to 0 EPIR02 Bit Bit...

Page 906: ...O number 1 cannot designate other than the maximum packed size of 8 bytes control transfer method and out transfer direction 2 The endpoint number 0 and the endpoint FIFO number must have one on one r...

Page 907: ...l In Out 8 bytes 0 1 1 0 0 Bulk Out 64 bytes 1 2 1 0 0 Bulk In 64 bytes 2 3 1 0 0 Interrupt In 8 bytes 3 1 1 0 1 1 1 N EPIR N 0 EPIR N 1 EPIR N 2 EPIR N 3 EPIR N 4 0 00 00 10 00 00 1 14 20 80 00 01 2...

Page 908: ...e R W Description 7 PTSTE 0 R W Pin Test Enable Enables the test control for the built in transceiver output pins USD and USD 6 to 4 All 0 R Reserved These bits are always read as 0 The initial value...

Page 909: ...at can monitor the built in transceiver input signal Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the built in transceiver input signal Table 22 5 shows the relationship between pi...

Page 910: ...Setting Pin Input TRNTREG1 Monitoring Value PTSTE SUSPEND VBUS USD USD xver_data dpls dmns Remarks 0 X X X X 0 0 0 Cannot be monitored when PTSTE 0 1 0 1 0 0 X 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0...

Page 911: ...SBINTN3 1 Control transfer EP0 EP0i_TR EP0i transfer request USBINTN2 or USBINTN3 2 EP0o_TS EP0o receive complete USBINTN2 or USBINTN3 3 SETUP_TS Setup command receive complete USBINTN2 or USBINTN3 4...

Page 912: ...upt signal only EP1 See section 22 8 DTC Transfer USBINTN1 signal DTC start interrupt signal only EP1 See section 22 8 DTC Transfer USBINTN2 signal The USBINTN2 signal requests interrupt sources for w...

Page 913: ...As soon as preparations are completed enable D pull up in general output port Clear VBUSF flag IFR1 VBUSF Firmware preparations for start of USB communication Clear bus reset flag IFR0 BRST Clear FIFO...

Page 914: ...100 22 5 2 Operation at Cable Disconnection USB function Application Cable connected VBUS pin 1 USB cable disconnection VBUS pin 0 UDC core reset End Figure 22 3 Operation at Cable Disconnection The a...

Page 915: ...occurs IFR2 SURSF 1 USBINT2 USBINT3 Remote wakeup enabled CTLR RWUPS 1 Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1 Clear SURSE in IER2 to 0 Wait for suspend resume interrupt Yes Yes N...

Page 916: ...d state Resume interrupts is requested from the up stream Suspend resume interrupt occurs IFR2 SURSF 1 RESUME Cancel software standby mode Clear SURSF in IFR2 to 0 Set SURSE in IER2 to 1 Clear SSRSME...

Page 917: ...FR2 to 1 USBINTN interrupt Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1 Clear SURSF in IER2 to 0 Set SSRSME in IER2 to 1 Shift to software standby mode execute SLEEP instruction Stop al...

Page 918: ...ing time USB bus state USBINTN interrupt SURSF SURSS SSRSME 1 RESUME interrupt Software standby Software standby Oscillator USB dedicated clock cku Peripheral module clock Normal Suspend Resume normal...

Page 919: ...l software standby mode Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0 Software standby mode USB module stopped Oscillation stabilization time has passed No No No Yes Yes Yes Start US...

Page 920: ...tatus figure 22 9 The data stage comprises a number of bus transactions Operation flowcharts for each stage are shown below Control in Setup stage Data stage Status stage Control out No data SETUP 0 D...

Page 921: ...ata stage direction 1 Write 1 to EP0s read complete bit TRG EP0s RDFN 1 To control in data stage To control out data stage Command to be processed by application Interrupt request Yes No Notes 1 In th...

Page 922: ...in the setup stage and determines the subsequent data stage direction If the result of command data analysis is that the data stage is in transfer one packet of data to be sent to the host is written...

Page 923: ...1 written to TRG EP0o RDFN NAK NAK ACK No Yes No Yes Interrupt request Figure 22 12 Data Stage Control Out Operation The application first analyzes command data from the host in the setup stage and de...

Page 924: ...rol transfer Set EP0o reception complete flag IFR0 EP0o TS 1 Clear EP0o reception complete flag IFR0 EP0o TS 0 Write 1 to EP0o read complete bit TRG EP0o RDFN 1 End of control transfer ACK Interrupt r...

Page 925: ...re 22 14 Status Stage Control Out Operation The control out status stage starts with an IN token from the host When an IN token is received at the start of the status stage there is not yet any data i...

Page 926: ...ransfer Operation EP1 has two 64 byte FIFOs but the user can receive data and read receive data without being aware of this dual FIFO configuration When one FIFO is full after reception is completed t...

Page 927: ...e bit TRG EP2 PKTE 1 Clear EP2 empty status TRG EP2 EMPTY 0 IN token reception Data transmission to host Interrupt request Interrupt request Application Transfer processing Resume Transfer data set pr...

Page 928: ...smitted is written to the data register using this interrupt After the first transmit data write for one FIFO the other FIFO is empty and so the next transmit data can be written to the other FIFO imm...

Page 929: ...Write data to EP3 data register EPDR3 Write 1 to EP3 packet enable bit TRG EP3 PKTE 1 Valid data in EP3FIFO Is there data for transmission to host Is there data for transmission to host No Yes No Yes...

Page 930: ...Interface Get Status Set Address Set Configuration Set Feature Set Interface Get Descriptor Class Vendor command Set Descriptor Sync Frame If decoding is not necessary on the application side command...

Page 931: ...int it sets the corresponding bit in EPSTL 1 1 in figure 22 18 The internal status bits are not changed at this time When a transaction is sent from the host for the endpoint for which the EPSTL bit w...

Page 932: ...T token received from host 2 EPSTL referenced 1 Transmission of STALL handshake 1 Internal status bit cleared to 0 1 Internal status bit cleared to 0 2 EPSTL not changed 1 1 set in EPSTL 2 Internal st...

Page 933: ...gure 22 19 To clear a stall therefore the internal status bit must be cleared with a Clear Feature command 3 1 in figure 22 19 If set by the application EPSTL should also be cleared 2 1 in figure 22 1...

Page 934: ...setting register to 1 zero length data reception at endpoint 1 is ignored When the DTC transfer is enabled the RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG note that the PK...

Page 935: ...r end interrupt If this procedure is omitted the DTC transfer end interrupt is not cleared To perform the DTC transfer again in addition to the said procedure set the number of transfers in the DTC se...

Page 936: ...et the number of transfers set the DTCERF register and then set the EP2DMAE bit in DMA to 1 Figure 22 21 shows an example for transmitting 150 bytes of data to the host In this case internal processin...

Page 937: ...truction should not be used for this setting When the DTC transfer is continuously performed Set CRA and CRB of the DTC the number of transfers Set the DTCERF register Set 1 to the EP1DMAE bit in DMA...

Page 938: ...ost hub connection notification D pill up is enabled 3 Detection of USB Cable Connection Disconnection As USB states etc are managed by hardware in this module a VBUS signal that recognizes connection...

Page 939: ...be applied voltage even when the system power is turned off Prevent noise from the VBUS pin while the USB is performing communication 3 3 V VBUS 5 V Vcc 3 3 V DrVCC 3 3 V USD D VBUS 2 PM4 Vcc 1 Vcc 1...

Page 940: ...ile a FIFO is transferring data it must not be cleared 22 10 3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module 1 Receive dat...

Page 941: ...to EP0i EP2 or EP3 The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host However at the timing shown in figure 22 24 multiple TR interrupts...

Page 942: ...as shown in table 22 8 Operation cannot be guaranteed if any frequency other than in the following table is specified When UXSEL is set to 0 connect USEXTAL to the system power supply 0 V The USB ope...

Page 943: ...channels Conversion time 4 7 s per channel at 34 MHz operation Two operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels or continuous A D c...

Page 944: ...D R A A D D R H A D D R G A D D R F A D D R E Successive approximations register Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B...

Page 945: ...t Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pins A D ex...

Page 946: ...R 23 3 1 A D Data Registers A to H ADDRA to ADDRH The ADDR are eight 16 bit read only registers ADDRA to ADDRH which store the results of A D conversion The ADDR registers which store a conversion res...

Page 947: ...tion of the A D conversion Bit Bit Name Initial Value R W Description 7 ADF 0 R W A D End Flag A status flag that indicates the end of A D conversion This flag indicates that the results of A D conver...

Page 948: ...andby mode 4 0 R Reserved This is a read only bit and cannot be modified 3 0 R W Reserved This bit is always read as 0 The initial value should not be changed Channel Select 2 to 0 Select analog input...

Page 949: ...ANE SCANS 0 0 R W R W Scan Mode Select the operation mode of A D conversion 0x Single mode 10 Scan mode consecutive A D conversion of channels 1 to 4 11 Scan mode consecutive A D conversion of channel...

Page 950: ...only once on the specified single channel Operations are as follows 1 A D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by software or by the input of trigger...

Page 951: ...follows 1 When the ADST bit in ADCSR is set to 1 by software or by the input of trigger signal A D conversion starts from the first channel of the selected channel Consecutive A D conversion of eithe...

Page 952: ...DDRD 2 Set 1 Clear 1 Clear 1 State of channel 0 AN0 State of channel 1 AN1 State of channel 2 AN2 State of channel 3 AN3 Idle Idle Idle Idle Idle Continuous execution of A D conversion Idle Idle Idle...

Page 953: ...3 4 show the A D conversion time As indicated in figure 23 4 the A D conversion time tCONV includes tD and the input sampling time tSPL The length of tD varies depending on the timing of the write acc...

Page 954: ...906 of 1178 REJ09B0403 0100 Address Write signal Input sampling timing ADF Legend 1 ADCSR write cycle 2 ADCSR address tD A D conversion start delay tSPL Input sampling time tCONV A D conversion time 2...

Page 955: ...ol Min Typ Max Min Typ Max Min Typ Max A D conversion start delay time tD 6 9 10 17 18 33 Input sampling time tSPL 30 60 120 A D conversion time tCONV 77 80 153 160 305 320 Note Values in the table ar...

Page 956: ...e signal on the ADTRG pin as an external trigger The ADST bit in ADCSR is set to 1 on the falling edge of ADTRG initiating A D conversion Other operations are the same as those in the case where the A...

Page 957: ...A D converter digital output codes Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure23 6 Offset error The deviation of the analog input voltage value from the...

Page 958: ...1024 FS Quantization error Digital output Ideal A D conversion characteristic Analog input voltage Figure 23 6 A D Conversion Accuracy Definitions FS Offset error Nonlinearity error Actual A D convers...

Page 959: ...citance to be charged within the sampling time if the sensor output impedance exceeds 5 k charging may be insufficient and it may not be possible to guarantee the A D conversion accuracy However if a...

Page 960: ...cc Vss The relationship between AVcc AVss and Vcc Vss should be Avcc Vcc 0 3V and AVss Vss When the A D converter is not used set AVcc Vcc and Avss Vss AVref pin reference voltage specification range...

Page 961: ...nput pins AN0 to AN7 are averaged which may cause an error Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and h...

Page 962: ...uit 23 7 7 Note on the Usage in Software Standby Mode If this LSI enters software standby mode with the A D conversion enabled the content of the A D converter is retained and about the same amount of...

Page 963: ...high speed static RAM The RAM is connected to the CPU by a 16 bit data bus enabling one state access by the CPU to both byte data and word data The on chip RAM can be enabled or disabled by means of t...

Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...

Page 965: ...Kbyte block Number of programming The number of flash memory programming can be up to 100 times at the minimum The value ranged from 1 to 100 is guaranteed Four on board programming modes SCI boot mod...

Page 966: ...l address bus Internal data bus 16 bits Legend FCCS Flash code control status register FPCS Flash program code select register FECS Flash erase code select register FKEY Flash key code register FMATS...

Page 967: ...h memory can be read programmed or erased on the board only in boot mode user program mode and user boot mode Flash memory can be read programmed or erased by means of the PROM programmer in programme...

Page 968: ...MAT 2 Transition to user mode Changing mode setting and reset Changing FLSHE bit and FWE pin Changing mode setting and reset Notes 1 All erasure is performed After that the specified block can be eras...

Page 969: ...er mode User MAT User Boot MAT Address H 000000 Address H 07FFFF Address H 000000 Address H 003FFF 512 Kbytes 16 Kbytes Figure 25 3 Flash Memory Configuration The size of the user MAT is different fro...

Page 970: ...01 H 006002 H 007000 H 007001 H 007002 H 040000 H 04F001 H 04F002 H 050000 H 050001 H 050002 H 000F80 H 000F81 H 000F82 H 001F80 H 001F81 H 001F82 H 002F80 H 002F81 H 002F82 H 003F80 H 003F81 H 003F82...

Page 971: ...ation Start user procedure program for programming erasing End user procedure program Yes Programming in 128 byte units or erasing in one block units downloaded program execution Download on chip prog...

Page 972: ...g erasing execution the FLSHE bit in STCR and the FWE pin must be set to 1 to transition to user program mode The program data programming destination address is specified in 128 byte units when progr...

Page 973: ...sing enable pin MD2 Input Sets operating mode of this LSI MD1 Input Sets operating mode of this LSI TxD1 Output Serial transmit data output used in SCI boot mode RxD1 Input Serial receive data input u...

Page 974: ...register FECS Flash key code register FKEY Flash MAT select register FMATS Flash transfer destination address register FTDAR Download pass fail result DPFR Flash pass fail result FPFR Flash multipurp...

Page 975: ...m ming Erasure Read FCCS FPCS FECS FKEY FMATS 1 1 2 Programming Erasing Interface Register FTDAR DPFR FPFR FPEFEQ FMPAR FMPDR Programming Erasing Interface Parameter FEBS Notes 1 The setting is requir...

Page 976: ...Flash Code Control Status Register FCCS FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of o...

Page 977: ...normally Programming erasing protection for flash memory error protection is invalid Clearing condition At a reset or in hardware standby mode 1 An error occurs during programming erasing flash memory...

Page 978: ...number 31 Therefore make sure to set the vector table in the on chip RAM space before setting this bit to 1 The interrupt exception handling on and after vector number 32 should not be used because th...

Page 979: ...hip RAM Four NOP instructions must be executed immediately after setting this bit to 1 Since this bit is cleared to 0 when download is completed this bit cannot be read as 1 All interrupts must be dis...

Page 980: ...amming program 0 On chip programming program is not selected Clearing condition When transfer is completed 1 On chip programming program is selected Flash Erase Code Select Register FECS FECS selects...

Page 981: ...K3 K2 K1 K0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Key Code Only when H A5 is written writing to the SCO bit is valid When the value other than H A5 is written to FKEY 1 cannot be set to the...

Page 982: ...the value in FMATS When the MAT is switched follow section 25 6 Switching between User MAT and User Boot MAT The user boot MAT cannot be programmed in user program mode if user boot MAT is selected b...

Page 983: ...o 0 before setting the SCO bit to 1 and the value specified by TDA6 to TDA0 is within the range of H 00 to H 03 0 The value specified by bits TDA6 to TDA0 is within the range 1 The value specified by...

Page 984: ...ation or on chip program is executed registers of the CPU except for R0L are stored The return value of the processing result is written in R0L Since the stack area is used for storing the registers e...

Page 985: ...t DPFR R W Undefined On chip RAM Flash pass fail result FPFR R W Undefined R0L of CPU Flash programming erasing frequency control FPEFEQ R W Undefined ER0 of CPU Flash multipurpose address area FMPAR...

Page 986: ...the certain determination must be performed by writing the single byte of the start address specified by FTDAR to the value other than the return value of download for example H FF before the downloa...

Page 987: ...ess Fail Returns the result whether download is ended normally or not The determination result whether program that is downloaded to the on chip RAM is read back and then transferred to the on chip RA...

Page 988: ...operating frequency in this LSI is 20 to 34 MHz Bit Bit Name Initial Value R W Description 31 to 16 Unused This bit should be cleared to 0 15 to 0 F15 to F0 R W Frequency Set Set the operating frequen...

Page 989: ...in which the program data is downloaded 1 The start address of the programming destination on the user MAT must be stored in a general register ER1 This parameter is called as flash multipurpose addr...

Page 990: ...the specified start address of the user MAT Therefore the specified programming start address becomes a 128 byte boundary and MOA6 to MOA0 are always 0 b Flash multipurpose data destination parameter...

Page 991: ...cution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased If this bit is set to 1 there is a high possibility that the user MAT is...

Page 992: ...tect When the following items are specified as the start address of the programming destination an error occurs When the programming destination address in the area other than flash memory is specifie...

Page 993: ...g procedure see section 25 4 3 User Program Mode a Flash erase block select parameter FEBS general register ER0 of CPU This parameter specifies the erase block number Bit Bit Name Initial Value R W De...

Page 994: ...l FWE 1 FLER 0 1 Programming cannot be performed FWE 0 or FLER 1 5 EE R W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash memory related re...

Page 995: ...4 On Board Programming Mode When the pin is set in on board programming mode and the reset start is executed the on board programming state that can program erase the on chip flash memory is entered...

Page 996: ...oot program in the microcomputer is initiated After the SCI bit rate is automatically adjusted the communication with the host is executed by means of the control command method The system configurati...

Page 997: ...normally boot mode is initiated again reset and the operation described above must be executed The bit rate between the host and this LSI is not matched by the bit rate of transmission by the host and...

Page 998: ...FFFF and transmitted Then the state for waiting program data is returned to the state of programming erasing command wait When the erasure preparation notice is received the state for waiting erase bl...

Page 999: ...t completed Bit rate adjustment Processing of inquiry setting command All user MAT and user boot MAT erasure Wait for program data Wait for erase block data Read check command reception Command respon...

Page 1000: ...or transmitting the control command and program data and the program data must be prepared in the host The system configuration in USB boot mode is shown in figure 25 9 Interrupts are ignored in USB b...

Page 1001: ...efer to table 25 7 Table 25 7 Enumeration Information USB standard Ver 2 0 Full speed Transfer mode Transfer mode Control in out Bulk in out Maximum power consumption 100 mA Endpoint configuration EP0...

Page 1002: ...mpletion Erasure selection command reception Program data transmission Processing of read check command Wait for inquiry programming erasing command Wait for inquiry programming erasing command Wait f...

Page 1003: ...rogramming erasing there are commands for performing sum check blank check erasure check and memory read of the user MAT and acquiring the current status information 3 Notes on USB Boot Mode Execution...

Page 1004: ...he reset input period of 100 s which is longer than normal When programming program data is prepared Programming erasing procedure program is transferred to the on chip RAM and executed Programming er...

Page 1005: ...ogram area to be downloaded System use area 15 bytes On chip RAM Address Area to be downloaded Size 3 Kbytes Unusable area in programming erasing processing period Area that can be used by user DPFR R...

Page 1006: ...Clear FKEY to 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 1 1 3 Download Initialization Programming Initialization JSR FTDAR setting 32 Initialization error processing Set parameters to ER1 and ER0 FMPAR and...

Page 1007: ...hen download is executed To set 1 to the SCO bit the following conditions must be satisfied H A5 is written to FKEY The SCO bit writing is executed in the on chip RAM When the SCO bit is set to 1 down...

Page 1008: ...and the download result must be confirmed Check the value of the DPFR parameter one byte of start address of the download destination specified by FTDAR If the value is H 00 download has been performe...

Page 1009: ...in the initialization program FPFR general register R0L is determined 9 All interrupts and the use of a bus master other than the CPU are prohibited The specified voltage is applied for the specified...

Page 1010: ...must be transferred to the on chip RAM and then programming must be executed 12 Programming There is an entry point of the programming program in the area from the start address specified by FTDAR 16...

Page 1011: ...bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Yes FPFR 0 No Clear FKEY and erasing error processing Yes Required block erasing is completed No Set FKEY to H 5A Clear FKEY to 0...

Page 1012: ...3 2 Programming Procedure in User Program Mode The procedures after setting parameters for erasing programs are as follows 2 Set the FEBS parameter necessary for erasure Set the erase block number of...

Page 1013: ...he erasing program and programming program can be downloaded to separate on chip RAM areas Figure 25 15 shows a repeating procedure of erasing and programming Yes No 1 1 Erasing program download Progr...

Page 1014: ...stack area are reserved in on chip RAM Do not make settings that will overwrite data in these areas Be sure to initialize both the erasing program and programming program Initialization by setting the...

Page 1015: ...rt is executed in user boot mode the built in check routine runs The user MAT and user boot MAT states are checked by this check routine While the check routine is running NMI and all other interrupts...

Page 1016: ...the programming error processing in the user boot MAT Start programming procedure program Select on chip program to be downloaded and specify download destination by FTDAR Figure 25 16 Procedure for P...

Page 1017: ...on in section 25 6 Switching between User MAT and User Boot MAT Except for MAT switching the programming procedure is the same as that in user program mode The area that can be executed in the steps o...

Page 1018: ...FEBS parameter Yes No Clear FKEY and erasing error processing Yes Required block erasing is completed No Set FKEY to H A5 Clear FKEY to 0 1 1 Download Initialization Erasing Set FMATS to value other t...

Page 1019: ...and if an interrupt occurs from which MAT the interrupt vector is read is undetermined Perform MAT switching in accordance with the description in section 25 6 Switching between User MAT and User Boo...

Page 1020: ...MI handler should be transferred to the on chip RAM before programming erasing of the flash memory starts 5 The flash memory is not accessible during programming erasing operations therefore the opera...

Page 1021: ...ration of these conditions there are three factors operating mode the bank structure of the user MAT and operations The areas in which the programming data can be stored for execution are shown in tab...

Page 1022: ...eration for Selection of On chip Program to be Downloaded Operation for Writing H A5 to FKEY Execution of Writing SCO 1 to FCCS Download Operation for FKEY Clear Determination of Download Result Opera...

Page 1023: ...Area Selected MAT Item On chip RAM User MAT External Space Expanded Mode User MAT Embedded Program Storage Area Execution of Programming Determination of Program Result Operation for Program Error Op...

Page 1024: ...be Downloaded Operation for Writing H A5 to FKEY Execution of Writing SCO 1 to FCCS Download Operation for FKEY Clear Determination of Download Result Operation for Download Error Operation for Setti...

Page 1025: ...0 Mar 12 2008 Page 977 of 1178 REJ09B0403 0100 Storable Executable Area Selected MAT Item On chip RAM User MAT External Space Expanded Mode User MAT Embedded Program Storage Area Operation for Erasure...

Page 1026: ...for Program Data 1 Operation for Selection of On chip Program to be Downloaded Operation for Writing H A5 to FKEY Execution of Writing SCO 1 to FCCS Download Operation for FKEY Clear Determination of...

Page 1027: ...T User Boot MAT Embedded Program Storage Area Operation for Settings of Program Parameter Execution of Programming Determination of Program Result Operation for Program Error 2 Operation for FKEY Clea...

Page 1028: ...Operation for Selection of On chip Program to be Downloaded Operation for Writing H A5 to FKEY Execution of Writing SCO 1 to FCCS Download Operation for FKEY Clear Determination of Download Result Op...

Page 1029: ...MAT External Space Expanded Mode User MAT User Boot MAT Embedded Program Storage Area Operation for Settings of Erasure Parameter Execution of Erasure Determination of Erasure Result Operation for Er...

Page 1030: ...ection 25 5 1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection In this state the downloading of an on chip program and initializatio...

Page 1031: ...ialized in the reset state including a reset by the WDT and standby mode and the program erase protected state is entered The reset state will not be entered by a reset using the RES pin unless the RE...

Page 1032: ...Protection Error protection is a mechanism for aborting programming or erasure when an error occurs in the form of the microcomputer entering runaway during programming erasing of the flash memory or...

Page 1033: ...ing the reset period so that the charge is released The state transition diagram in figure 25 18 shows transitions to and from the error protection state Reset or hardware standby Hardware protection...

Page 1034: ...the system so that NMI interrupts do not occur during MAT switching 4 After the MATs have been switched take care because the interrupt vector table will also have been switched If interrupt processi...

Page 1035: ...d user boot MAT 1 The PROM programmer must support microcomputers with 256 or 512 Kbyte flash memory as a device type 2 A status polling system is adopted for operation in automatic program automatic...

Page 1036: ...e bit rate the program enters the inquiry selection state 2 Inquiry Selection State In this state the boot program responds to inquiry commands from the host The device name clock mode and bit rate ar...

Page 1037: ...ing wait Checking Inquiry Response Erasing Programming Reset Bit rate adjustment state Operations for erasing user MATs and user boot MATs Operations for inquiry and selection Operations for programmi...

Page 1038: ...rror Figure 25 21 Bit Rate Adjustment Sequence 3 Communications Protocol After adjustment of the bit rate the protocol for communications between the host and the boot program is as shown below 1 1 by...

Page 1039: ...onse Data Checksum Memory read response Figure 25 22 Communication Protocol Format Command 1 byte Commands including inquiries selection programming erasing and checking Response 1 byte Response to an...

Page 1040: ...regarding the number of frequency multiplied clock types the number of multiplication ratios and the values of each multiple H 23 Operating Clock Frequency Inquiry Inquiry regarding the maximum and m...

Page 1041: ...program will return the device codes of supported devices and the product code in response to the supported device inquiry Command H 20 Command H 20 1 byte Inquiry regarding supported devices Response...

Page 1042: ...ed when the device code matches Error response H 90 ERROR Error response H 90 1 byte Error response to the device selection command ERROR 1 byte Error code H 11 Sum check error H 21 Device code error...

Page 1043: ...Amount of data that represents the modes Mode 1 byte A clock mode returned in reply to the supported clock mode inquiry SUM 1 byte Checksum Response H 06 Response H 06 1 byte Response to the clock mod...

Page 1044: ...there are two multiplied clock types which are the main and peripheral clocks the number of types will be H 02 Number of multiplication ratios 1 byte The number of multiplication ratios for each type...

Page 1045: ...ues maximum values and the number of frequencies Number of operating clock frequencies 1 byte The number of supported operating clock frequency types e g when there are two operating clock frequency t...

Page 1046: ...eas returned is H 01 Area start address 4 byte Start address of the area Area last address 4 byte Last address of the area There are as many groups of data representing the start and last addresses as...

Page 1047: ...s that represents the number of blocks block start addresses and block last addresses Number of blocks 1 byte The number of erased blocks Block start address 4 bytes Start address of a block Block las...

Page 1048: ...f multiplication ratios 1 byte The number of multiplication ratios to which the device can be set Multiplication ratio 1 1 byte The value of multiplication or division ratios for the main operating fr...

Page 1049: ...the specified device When the value is out of this range an input frequency error is generated 2 Multiplication ratio The received value of the multiplication ratio or division ratio is checked to en...

Page 1050: ...64 2 2 n 1 106 When the new bit rate is selectable the rate will be set in the register after sending ACK in response The host will send an ACK with the new bit rate for confirmation and the boot pro...

Page 1051: ...mmand H 40 Command H 40 1 byte Transition to programming erasing state Response H 06 Response H 06 1 byte Response to transition to programming erasing state The boot program will send ACK when the us...

Page 1052: ...inquiries for other required information should be made such as the multiplication ratio inquiry H 22 or operating frequency inquiry H 23 which are needed for a new bit rate selection 6 A new bit rat...

Page 1053: ...ection Transfers the user boot MAT programming program H 43 User MAT programming selection Transfers the user MAT programming program H 50 128 byte programming Programs 128 bytes of data H 48 Erasing...

Page 1054: ...he data programmed according to the method specified by the selection command When more than 128 byte data is programmed 128 byte commands should repeatedly be executed Sending a 128 byte programming...

Page 1055: ...ccurs and processing is not completed User MAT programming selection The boot program will transfer a program for programming The data is programmed to the user MATs by the transferred program for pro...

Page 1056: ...r H 2A Address Error H 53 Programming error A programming error has occurred and programming cannot be continued The specified address should match the unit for programming of data For example when th...

Page 1057: ...by the erasure selection command and the boot program then erases the specified block The command should be repeatedly executed if two or more blocks are to be erased Sending a block erasure command f...

Page 1058: ...tion processing error transfer error occurs and processing is not completed b Block Erasure The boot program will erase the contents of the specified block Command H 58 Size Block number SUM Command H...

Page 1059: ...the procedure should be executed from the erasure selection command 11 Memory read The boot program will return the data in the specified address Command H 52 Size Area Read address Read size SUM Comm...

Page 1060: ...to the sum check of user boot MAT Size 1 byte The number of bytes that represents the checksum This is fixed to 4 Checksum of user boot program 4 bytes Checksum of user boot MATs The total of the dat...

Page 1061: ...e H CC H 52 Error Response H CC 1 byte Response to blank check for user boot MAT Error Code H 52 1 byte Erasure has not been completed 15 User MAT Blank Check The boot program will check whether or no...

Page 1062: ...inquiry Size 1 byte The number of bytes This is fixed to 2 Status 1 byte State of the boot program ERROR 1 byte Error status ERROR 0 indicates normal operation ERROR 1 indicates error has occurred SUM...

Page 1063: ...smatch Error H 22 Clock Mode Mismatch Error H 24 Bit Rate Selection Error H 25 Input Frequency Error H 26 Multiplication Ratio Error H 27 Operating Frequency Error H 29 Block Number Error H 2A Address...

Page 1064: ...he reset input period of 100 s which is longer than normal 6 The flash memory is not accessible until FKEY is cleared after programming erasing completes If this LSI is restarted by a reset immediatel...

Page 1065: ...am takes approximately 180 s at the maximum 13 While an instruction in on chip RAM is being executed the DTC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used...

Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...

Page 1067: ...e name of the group who worked on standardization is the JTAG the JTAG is commonly used as the name of a boundary scan architecture and a serial interface to access the devices having the architecture...

Page 1068: ...020 of 1178 REJ09B0403 0100 TAP controller ETCK ETMS ETRST ETDO Mux SDIR Decoder SDBPR SDIR Legend SDBPR SDBSR SDIDR Instruction register Bypass register Boundary scan register ID code register ETDI S...

Page 1069: ...ct input Sampled on the rise of the ETCK pin The ETMS pin controls the internal state of the TAP controller If there is no input the ETMS pin is fixed to 1 by an internal pull up Test data input ETDI...

Page 1070: ...which the ETDI and ETDO pins are connected in BYPASS CLAMP or HIGHZ mode The boundary scan register SDBSR is a 346 bit register in H8S 2472 group 333 bit register in H8S 2462 group to which the ETDI a...

Page 1071: ...Bit Bit Name Initial Value R W Description 31 30 29 28 TS3 TS2 TS1 TS0 1 1 1 0 R W R W R W R W Test Set Bits 0000 EXTEST mode 0001 Setting prohibited 0010 CLAMP mode 0011 HIGHZ mode 0100 SAMPLE PRELOA...

Page 1072: ...R is connected between the ETDI and ETDO pins 26 3 3 Boundary Scan Register SDBSR SDBSR is a shift register provided on the PAD for controlling the I O pins of this LSI Using EXTEST mode or SAMPLE PRE...

Page 1073: ...328 E3 PF6 Output 327 Input 326 A1 VCC E2 NMI Input 345 Enable 344 C3 P45 Output 343 E1 STBY Input 342 Enable 341 B1 P46 Output 340 F4 NC Input 339 Enable 338 C2 P47 Output 337 F3 VCL Input 336 Input...

Page 1074: ...tput 307 K1 PC4 Output 283 Input 306 Input 282 Enable 305 Enable 281 H3 P93 Output 304 K2 PC3 Output 280 H1 NC L3 NC Input 303 Input 279 Enable 302 Enable 278 H2 P92 Output 301 L1 PC2 Output 277 Input...

Page 1075: ...3 M4 PA5 Output 262 P4 NC N2 VCC M5 VSS Input 261 Enable 260 P1 PA4 Output 259 R4 NC Input 258 Input 246 Enable 257 Enable 245 P2 PA3 Output 256 N5 P87 Output 244 Input 243 Enable 242 R1 NC P5 P86 Out...

Page 1076: ...CC Input 222 Input 198 Enable 221 Enable 197 R7 PE7 Output 220 M10 PD7 Output 196 Input 195 Enable 194 P7 NC N10 PD6 Output 193 Input 219 Input 192 Enable 218 Enable 191 M8 PE6 Output 217 R10 PD5 Outp...

Page 1077: ...CC P12 AVSS N14 AVref Input 174 Input 166 Enable 165 N12 P70 M13 P60 Output 164 Input 173 Input 163 Enable 162 R13 P71 N15 P61 Output 161 Input 172 Input 160 Enable 159 M12 P72 M14 P62 Output 158 Inpu...

Page 1078: ...Bit No Input 145 Enable 144 L15 P67 Output 143 H13 ETDO K12 VCC H15 ETDI K13 DrVCC H14 ETCK K15 USD G12 ETRST Input 141 Enable 140 K14 USD G13 PF2 Output 139 Input 138 Enable 137 J12 NC G15 PF1 Output...

Page 1079: ...2 E15 P24 Output 121 B14 P12 Output 91 Input 120 Input 90 Enable 119 Enable 89 E14 P23 Output 118 A15 P11 Output 88 Input 117 Enable 116 E12 P22 Output 115 C13 VSS Input 114 Input 87 Enable 113 Enable...

Page 1080: ...0 Input 66 Input 39 Enable 65 Enable 38 C11 PB1 Output 64 B9 P37 Output 37 Input 63 Input 36 Enable 62 Enable 35 B11 PB0 Output 61 D8 P40 Output 34 Input 33 Enable 32 A11 VCC C8 P41 Output 31 Input 60...

Page 1081: ...t Bit No Input 21 Input 8 Enable 20 Enable 7 B7 P53 Output 19 A4 PF5 Output 6 Input 18 Input 5 Enable 4 D6 FWE B4 PF4 Output 3 Input 17 Enable 16 C6 P54 Output 15 C4 NC Input 14 Enable 13 A6 P55 Outpu...

Page 1082: ...utput 314 Input 313 1 VCC 11 NMI Input 332 Enable 331 2 P45 Output 330 12 STBY Input 329 Enable 328 3 P46 Output 327 13 VCL Input 326 Input 312 Enable 325 4 P47 Output 324 14 MD2 Input 323 Input 311 E...

Page 1083: ...59 22 P92 Output 288 32 PC0 Output 258 Input 287 Input 257 Enable 286 Enable 256 23 P91 Output 285 33 PA7 Output 255 Input 284 Input 254 Enable 283 Enable 253 24 P90 Output 282 34 PA6 Output 252 Input...

Page 1084: ...ut 204 Input 233 Input 203 Enable 232 Enable 202 43 P87 Output 231 53 PE5 Output 201 Input 230 Input 200 Enable 229 Enable 199 44 P86 Output 228 54 PE4 Output 198 Input 227 Input 197 Enable 226 Enable...

Page 1085: ...nable 178 61 PD5 Output 177 71 P73 Input 176 Input 157 Enable 175 62 PD4 Output 174 72 P74 Input 173 Input 156 Enable 172 63 PD3 Output 171 73 P75 Input 170 Input 155 Enable 169 64 PD2 Output 168 74 P...

Page 1086: ...41 Input 129 Enable 140 Enable 128 82 P64 Output 139 92 PF1 Output 127 Input 138 Input 126 Enable 137 Enable 125 83 P65 Output 136 93 PF0 Output 124 Input 135 Enable 134 84 P66 Output 133 94 VSS Input...

Page 1087: ...00 112 PB7 Output 73 Input 99 Input 72 Enable 98 Enable 71 103 P17 Output 97 113 PB6 Output 70 Input 96 Input 69 Enable 95 Enable 68 104 P16 Output 94 114 PB5 Output 67 Input 93 Input 66 Enable 92 Ena...

Page 1088: ...47 Enable 17 122 P31 Output 46 132 P43 Output 16 Input 45 Enable 44 123 P32 Output 43 133 PEVref Input 42 Enable 41 124 P33 Output 40 134 PECI Input 39 Input 15 Enable 38 Enable 14 125 P34 Output 37...

Page 1089: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1041 of 1178 REJ09B0403 0100 Pin No Pin Name Input Output Bit No Input 2 Enable 1 140 P44 Output 0 141 VSS 142 RESO 143 XTAL 144 EXTAL to ETDO...

Page 1090: ...DIDR SDIDR is a 32 bit register In IDCODE mode SDIDR can output a fixed code H 0803D447 from the ETDO pin However no serial data can be written to SDIDR via the ETDI pin 31 28 27 12 11 1 0 0000 1000 0...

Page 1091: ...ates of the TAP controller State transitions basically conform to the IEEE1149 1 standard Test logic reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR scan Run test idle 1 0 0 0...

Page 1092: ...o effect on the system circuits 2 SAMPLE PRELOAD Instruction code B 0100 The SAMPLE PRELOAD instruction inputs values from this LSI internal circuitry to the boundary scan register outputs values from...

Page 1093: ...o the output pin boundary scan register in the Capture DR state is not used for external circuit testing it is replaced by a shift operation 4 CLAMP Instruction code B 0010 When the CLAMP instruction...

Page 1094: ...t Logic Reset state the instruction register is initialized to the IDCODE instruction Notes 1 Boundary scan mode does not cover power supply related pins VCC VCL VSS AVCC AVSS Avref PEVref DrVCC DrVSS...

Page 1095: ...the high impedance state These pins are internally pulled up and are noted in standby mode 2 The following must be considered when the power on reset signal is applied to the ETRST pin The reset signa...

Page 1096: ...transfer sequence is disrupted the ETRST pin must be reset Transfer should then be retried regardless of the transfer operation 8 If a pin with a pull up function is sampled while its pull up function...

Page 1097: ...captured into the shift register in Capture DR in IDCODE mode and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift DR Data input from the ETDI pin is not written to any regis...

Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...

Page 1099: ...l modules Bus master clock to CPU and DTC System clock select circuit Medium speed clock divider Bus master clock select circuit Figure 27 1 Block Diagram of Clock Pulse Generator The bus master clock...

Page 1100: ...esistance Rd given in table 27 1 should be used An AT cut parallel resonance crystal resonator should be used Figure 27 3 shows the equivalent circuit of a crystal resonator A crystal resonator having...

Page 1101: ...y mode EXTAL XTAL External clock input Open a Example of external clock input when XTAL pin left open EXTAL XTAL External clock input b Example of external clock input when an inverted clock is input...

Page 1102: ...aster Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock or medium speed clock 2 4 8 16 or 32 by the SCK2 to SCK0 bits in SB...

Page 1103: ...The clock select circuit selects the system clock that is used in this LSI A clock generated by the oscillator to which the EXTAL and XTAL pins are input and multiplied by the PLL circuit is selected...

Page 1104: ...ied to the oscillation pins do not exceed the maximum rating 27 8 2 Notes on Board Design When using a crystal resonator the crystal resonator and its load capacitors should be placed as close as poss...

Page 1105: ...n can be achieved by individually stopping on chip peripheral modules Medium speed mode System clock frequency for the CPU operation can be selected as 2 4 8 16 or 32 Sleep mode The CPU stops but on c...

Page 1106: ...Module stop control register H MSTPCRH Module stop control register L MSTPCRL Module stop control register A MSTPCRA Sub chip module stop control register BH BL SUBMSTPBH SUBMSTPBL 28 1 1 Standby Cont...

Page 1107: ...s the relationship between the STS2 to STS0 values and wait time 3 DTSPEED 0 R W DTC Speed Specifies the operating clock for the bus masters DTC other than the CPU in medium speed mode 0 All bus maste...

Page 1108: ...e STS2 STS1 STS0 Wait Time 20MHz 25MHz 34MHz Unit 0 0 0 8192 states 0 4 0 3 0 2 0 0 1 16384 states 0 8 0 7 0 5 0 1 0 32768 states 1 6 1 3 1 0 0 1 1 65536 states 3 3 2 6 1 9 1 0 0 131072 states 6 6 5 2...

Page 1109: ...clock 1 Sampling using 4 clock 4 EXCLE 0 R W Subclock Input Enable Enables disables subclock input from the EXCL pin 0 Disables subclock input from the EXCL pin 1 Enables subclock input from the EXCL...

Page 1110: ...ree running timer FRT 4 MSTP12 1 R W 8 bit timers TMR_0 TMR_1 3 MSTP11 1 R W 14 bit PWM timer PWMX 2 MSTP10 1 R W Reserved The initial value should not be changed 1 MSTP9 1 R W A D converter 0 MSTP8 1...

Page 1111: ...PWMX_0 0 MSTPA0 0 R W Reserved The initial value should not be changed MSTPCR sets operation and stop by the combination of bits as follows MSTPCRH bit 3 MSTP11 MSTPCRA bit 2 MSTPA2 Function 0 0 14 b...

Page 1112: ...troller EtherC 5 SMSTPB13 1 R W DMAC for Ethernet E DMAC 4 SMSTPB12 1 R W USB function module USB This bit is valid only in the H8S 2472 Group The initial value should not be changed in the H8S 2462 G...

Page 1113: ...ate Table 28 2 shows the LSI internal states in each operating mode Program halt state Program execution state SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 SLEEP instruction SLEEP instruction External in...

Page 1114: ...ules DTC Functioning Functioning in medium speed mode Functioning Functioning Functioning Halted retained Halted retained Halted reset WDT_1 Functioning Functioning WDT_0 TMR_0 TMR_1 LPC Functioning H...

Page 1115: ...r example if 4 is selected as the operating clock on chip memory is accessed in 4 states and internal I O registers in 8 states By clearing all of bits SCK2 to SCK0 to 0 a transition is made to high s...

Page 1116: ...ral modules do not stop The contents of the CPU s internal registers are retained Sleep mode is exited by any interrupt the RES pin or the STBY pin When an interrupt occurs sleep mode is exited and in...

Page 1117: ...the corresponding enable bit to 1 and ensure that any interrupt with a higher priority than IRQ0 to IRQ15 is not generated Software standby mode is not exited if the corresponding enable bit is clear...

Page 1118: ...of 1178 REJ09B0403 0100 Oscillator NMI NMIEG SSBY NMI exception handling NMIEG 1 SSBY 1 SLEEP instruction Software standby mode power down mode Oscillation stabilization time tOSC2 NMI exception hand...

Page 1119: ...before driving the STBY pin low Do not change the state of the mode pins MD2 and MD1 while this LSI is in hardware standby mode Hardware standby mode is cleared by the STBY pin input or the RES pin i...

Page 1120: ...heral module is in module stop mode read write access to its registers is disabled 28 8 Usage Notes 28 8 1 I O Port Status The status of the I O ports is retained in software standby mode Therefore wh...

Page 1121: ...igurations of the registers are described in the same order as the Register Addresses address order above Reserved bits are indicated by in the bit name column The bit number in the bit name column in...

Page 1122: ...gh register MAHR 32 H F910 EtherC 16 8 MAC address low register MALR 32 H F914 EtherC 16 8 Receive frame length register RFLR 32 H F918 EtherC 16 8 PHY status register PSR 32 H F91C EtherC 16 8 Transm...

Page 1123: ...ermission register EESIPR 32 H F998 E DMAC 16 8 Transmit receive status copy enable register TRSCER 32 H F99C E DMAC 16 8 Receive missed frame counter register RMFCR 32 H F9A0 E DMAC 16 8 Transmit FIF...

Page 1124: ...6 4 EP0s data register EPDR0s 8 H FA0E USB 16 4 EP1 data register EPDR1 8 H FA10 USB 16 4 EP2 data register EPDR2 8 H FA14 USB 16 4 EP3 data register EPDR3 8 H FA18 USB 16 4 EP0o receive data size reg...

Page 1125: ...CIF 16 2 SS control register H SSCRH 8 H FCC0 SSU 16 2 SS control register L SSCRL 8 H FCC1 SSU 16 2 SS mode register SSMR 8 H FCC2 SSU 16 2 SS enable register SSER 8 H FCC3 SSU 16 2 SS status registe...

Page 1126: ...l data register 0MW TWR0MW 8 H FD10 LPC 16 2 Bidirectional data register 0SW TWR0SW 8 H FD10 LPC 16 2 Bidirectional data register 1 TWR1 8 H FD11 LPC 16 2 Bidirectional data register 2 TWR2 8 H FD12 L...

Page 1127: ...D2C LPC 16 2 Output data register 2 ODR2 8 H FD2D LPC 16 2 Status register 2 STR2 8 H FD2E LPC 16 2 Host interface select register HISEL 8 H FD2F LPC 16 2 Host interface control register 0 HICR0 8 H F...

Page 1128: ...PFPIN 8 H FE4B PORT 8 2 Port F data direction register PFDDR 8 H FE4B PORT 8 2 Port C output data register PCODR 8 H FE4C PORT 8 2 Port D output data register PDODR 8 H FE4D PORT 8 2 Port C input data...

Page 1129: ..._1 SCR_1 8 H FE9A SCI_1 8 2 Transmit data register_1 TDR_1 8 H FE9B SCI_1 8 2 Serial status register_1 SSR_1 8 H FE9C SCI_1 8 2 Receive data register_1 RDR_1 8 H FE9D SCI_1 8 2 Smart card mode registe...

Page 1130: ...IIC_2 8 2 Second slave address register_2 SARX_2 8 H FECA IIC_2 8 2 I 2 C bus mode register_2 ICMR_2 8 H FECB IIC_2 8 2 Slave address register_2 SAR_2 8 H FECB IIC_2 8 2 PWMX D A data register A_1 DA...

Page 1131: ...H FEEF DTC 8 2 DTC enable register C DTCERC 8 H FEF0 DTC 8 2 DTC enable register D DTCERD 8 H FEF1 DTC 8 2 DTC enable register E DTCERE 8 H FEF2 DTC 8 2 DTC vector register DTVECR 8 H FEF3 DTC 8 2 Add...

Page 1132: ...register _1 SAR_1 8 H FF8F IIC_1 8 2 Timer interrupt enable register TIER 8 H FF90 FRT 8 2 Timer control status register TCSR 8 H FF91 FRT 8 2 Free running counter FRC 16 H FF92 FRT 16 2 Output compa...

Page 1133: ...B4 PORT 8 2 Port 4 data direction register P4DDR 8 H FFB5 PORT 8 2 Port 3 data register P3DR 8 H FFB6 PORT 8 2 Port 4 data register P4DR 8 H FFB7 PORT 8 2 Port 5 data direction register P5DDR 8 H FFB8...

Page 1134: ...8 2 Timer counter_1 TCNT_1 8 H FFD1 TMR_1 8 2 I 2 C bus control register_0 ICCR_0 8 H FFD8 IIC_0 8 2 I 2 C bus status register_0 ICSR_0 8 H FFD9 IIC_0 8 2 I 2 C bus data register_0 ICDR_0 8 H FFDE II...

Page 1135: ...FF1 TMR_X 8 2 Timer counter_X TCNT_X 8 H FFF4 TMR_X 8 2 Time constant register A_X TCORA_X 8 H FFF6 TMR_X 8 2 Time constant register B_X TCORB_X 8 H FFF7 TMR_X 8 2 Timer control register_Y TCR_Y 8 H F...

Page 1136: ...lines respectively Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ZPF PFR RXF TXF PRCEF MPDE ECMR RE TE ILB ELB DM PRM ECSR PSRTO LCHNG MPD ICD ECSIPR PSRTOIP LCHNGIP MPD...

Page 1137: ...OSDC3 COSDC2 COSDC1 COSDC0 LCC31 LCC30 LCC29 LCC28 LCC27 LCC26 LCC25 LCC24 LCC23 LCC22 LCC21 LCC20 LCC19 LCC18 LCC17 LCC16 LCC15 LCC14 LCC13 LCC12 LCC11 LCC10 LCC9 LCC8 LCCR LCC7 LCC6 LCC5 LCC4 LCC3 L...

Page 1138: ...LFC5 TLFC4 TLFC3 TLFC2 TLFC1 TLFC0 RFC31 RFC30 RFC29 RFC28 RFC27 RFC26 RFC25 RFC24 RFC23 RFC22 RFC21 RFC20 RFC19 RFC18 RFC17 RFC16 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFCR RFC7 RFC6 RFC5 RFC...

Page 1139: ...6 TDLA5 TDLA4 TDLA3 TDLA2 TDLA1 TDLA0 RDLA31 RDLA30 RDLA29 RDLA28 RDLA27 RDLA26 RDLA25 RDLA24 RDLA23 RDLA22 RDLA21 RDLA20 RDLA19 RDLA18 RDLA17 RDLA16 RDLA15 RDLA14 RDLA13 RDLA12 RDLA11 RDLA10 RDLA9 RD...

Page 1140: ...FD0 FDR RFD2 RFD1 RFD0 RMCR RNC RFF2 RFF1 RFF0 FCFTR RFD2 RFD1 RFD0 TRIMD TIS RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16 RBWA15 RBW...

Page 1141: ...FA1 TDFA0 ECBRR RTM IFR0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR EP0iTS IFR1 VBUSMN EP3TR EP3TS VBUSF IFR2 SURSS SURSF CFDN SETC SETI IER0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR E...

Page 1142: ...RCVRTRIG1 RCVRTRIG0 DMAMODE XMITFRST RCVRFRST FIFOE FLCR DLAB BREAK STICKPARITY EPS PEN STOP CLS1 CLS0 FMCR LOOPBACK OUT2 OUT1 RTS DTR FLSR RXFIFOERR TEMT THRE BI FE PE OE DR FMSR DCD RI DSR CTS DDCD...

Page 1143: ...CLR_WR_ PTR BTIMSR BMC_ HWRST OEM3 OEM2 OEM1 B2H_IRQ B2H_IRQ_ EN SMICFLG RX_DATA_ RDY TX_DATA_ RDY SMI SEVT_ATN SMS_ATN BUSY HICR5 SCIFE SMICCSR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMICDTR...

Page 1144: ...BU32 IBF3A OBF3A SIRQCR4 IRQ15E IRQ14E IRQ13E IRQ8E IRQ7E IRQ5E IRQ4E IRQ3E LADR3H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 LADR3L bit 7 bit 6 bit 5 bit 4 bit 3 bit 1 TWRE SIRQCR0 Q C SEL...

Page 1145: ...C MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPA0 P3NCE P37NCE P36NCE P35NCE P34NCE P33NCE P32NCE P31NCE P30NCE P3NCMC P37NCMC P36NCMC P35NCMC P34NCMC P33NCMC P32NCMC P31NCMC P3...

Page 1146: ...1 CKS0 BC2 BC1 BC0 SAR_4 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS IIC_4 ICCR_5 ICE IEIC MST TRS ACKE BBSY IRIC SCP ICSR_5 ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDR_5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi...

Page 1147: ...AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADCSR ADF ADIE ADST CH2 CH1 CH0 ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 ADSTCLR EXTRGS ADC SMR0 DCD1 RI1 DSR1 SME SM2 SM1 SM0 SMR1 CTS1 DTR1 RTS1 CTS3 RTS3 SMX P4BNCE P...

Page 1148: ...OS CKS DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DADRB_1 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS UC7 UC6 UC5 UC4 UC3 UC2 UC1 UC0 DACNT_1 UC8 UC9 UC10 UC11 UC12 UC13 REGS PWMX_1 CRCCR DORCLR LMS G1 G0 CRCDIR bit 7...

Page 1149: ...CEE3 DTCEE2 DTCEE1 DTCEE0 DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 DTC ABRKCR CMF BIE BARA A23 A22 A21 A20 A19 A18 A17 A16 BARB A15 A14 A13 A12 A11 A10 A9 A8 BARC A7 A6 A5 A4 A3 A...

Page 1150: ...it 2 bit 1 bit 0 OCRA bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCRB bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5...

Page 1151: ...P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR P4DR P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR P5DDR P57DDR P56DDR P55DDR P54DDR P53DDR P52D...

Page 1152: ...bit 3 bit 2 bit 1 bit 0 TMR_0 1 ICCR_0 ICE IEIC MST TRS ACKE BBSY IRIC SCP ICSR_0 ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDR_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SARX_0 SVAX6 SVAX5 SVAX4 S...

Page 1153: ...bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCR_Y CMIEB CMIEA OVIE CKS2 CKS1 CKS0 TCSR_Y CMFB CMFA OVF TCORA_Y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCORB_Y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1...

Page 1154: ...ed Initialized Initialized CDCR Initialized Initialized Initialized LCCR Initialized Initialized Initialized CNDCR Initialized Initialized Initialized CEFCR Initialized Initialized Initialized FRECR I...

Page 1155: ...ized Initialized RDFAR Initialized Initialized Initialized TBRAR Initialized Initialized Initialized TDFAR Initialized Initialized Initialized ECBRR Initialized Initialized Initialized IFR0 Initialize...

Page 1156: ...nitialized TRNTREG0 Initialized Initialized Initialized TRNTREG1 Initialized Initialized Initialized FRBR Initialized Initialized Initialized FTHR Initialized Initialized Initialized FDLL Initialized...

Page 1157: ...ialized Initialized Initialized SSRDR2 Initialized Initialized Initialized SSRDR3 Initialized Initialized Initialized SSTRSR Initialized Initialized Initialized HICR4 Initialized Initialized Initializ...

Page 1158: ...TWR14 TWR15 IDR3 ODR3 STR3 Initialized Initialized Initialized SIRQCR4 Initialized Initialized Initialized LADR3H Initialized Initialized Initialized LADR3L Initialized Initialized Initialized SIRQCR0...

Page 1159: ...DR12L Initialized Initialized Initialized SCIFADRH Initialized Initialized Initialized SCIFADRL Initialized Initialized Initialized SUBMSTPBH Initialized Initialized Initialized SYSTEM SUBMSTPBL Initi...

Page 1160: ...itialized ICSR_4 Initialized Initialized Initialized ICDR_4 SARX_4 Initialized Initialized Initialized ICMR_4 Initialized Initialized Initialized SAR_4 Initialized Initialized Initialized IIC_4 ICCR_5...

Page 1161: ...ized Initialized Initialized Initialized Initialized ADCR Initialized Initialized Initialized Initialized Initialized SMR0 Initialized Initialized Initialized SMR1 Initialized Initialized Initialized...

Page 1162: ...ialized Initialized Initialized IIC ICXR_2 Initialized Initialized Initialized IIC_2 ICXR_3 Initialized Initialized Initialized IIC_3 IICX3 Initialized Initialized Initialized IIC ICXR_4 Initialized I...

Page 1163: ...TCNT0 Initialized Initialized Initialized BCR2 Initialized Initialized Initialized WSCR2 Initialized Initialized Initialized BSC PCSR Initialized Initialized Initialized PWMX_0 1 SYSCR2 Initialized In...

Page 1164: ...Initialized TCSR_0 Initialized Initialized Initialized TCNT_0 Initialized Initialized Initialized WDT_0 PAODR Initialized Initialized Initialized PORT PAPIN PADDR Initialized Initialized Initialized P...

Page 1165: ...lized Initialized SYSTEM BCR Initialized Initialized Initialized BSC WSCR Initialized Initialized Initialized TCR_0 Initialized Initialized Initialized TCR_1 Initialized Initialized Initialized TCSR_0...

Page 1166: ...ed Initialized Initialized Initialized Initialized SCMR_3 Initialized Initialized Initialized SCI_3 TCSR_1 Initialized Initialized Initialized TCNT_1 Initialized Initialized Initialized WDT_1 TCR_X In...

Page 1167: ...I Renesas Technology Corporation is only able to provide information contained in this section to the parties with which we have concluded a nondisclosure agreement Please contact one of our sales rep...

Page 1168: ...Section 30 Platform Environment Control Interface PECI Rev 1 00 Mar 12 2008 Page 1120 of 1178 REJ09B0403 0100...

Page 1169: ...s other than 1 and 2 above Vin 0 3 to VCC 0 3 Reference power supply voltage AVref 0 3 to AVCC 0 3 Analog power supply voltage AVCC 0 3 to 4 3 Analog input voltage VAN 0 3 to AVCC 0 3 PECI reference p...

Page 1170: ...Item Symbol Min Typ Max Unit Test Conditions VT VCC 0 2 VT VCC 0 7 EVENT15 to EVENT0 Ex DB7 to Ex DB0 Ex IRQ15 to Ex IRQ0 ETRST XTAL EXCL ADTRG UXTAL UEXTAL VT VT VCC 0 05 VT VCC 0 3 VT VCC 0 7 Schmi...

Page 1171: ...low voltage Input pins other than 1 and 3 above VIL 0 3 VCC 0 2 SCL5 to SCL0 SDA5 to SDA0 CLKRUN GA20 PME LSMI LSCI 2 V Ports 80 to 83 C0 to C5 D6 D7 0 5 IOH 200 A SERIRQ LAD3 to LAD0 VCC 0 9 IOH 0 5...

Page 1172: ...input pin Cin 10 pF Vin 0 V f 1 MHz Ta 25 C RAM standby voltage VRAM 3 0 V VCC start voltage VCCSTART 0 0 8 V VCC rising edge SVCC 20 ms V Notes 1 Do not leave the AVCC AVref and AVSS pins open even i...

Page 1173: ...IOL 1 6 Total of HC7 to HC0 48 Permissible output low current total Total of all output pins including the above IOL 90 Permissible output high current per pin All output pins IOH 2 Permissible outpu...

Page 1174: ...Section 31 Electrical Characteristics Rev 1 00 Mar 12 2008 Page 1126 of 1178 REJ09B0403 0100 This LSI Ports 1 to 3 LED 600 Figure 31 2 LED Drive Circuit Example...

Page 1175: ...lock output and clock pulse generator crystal and external clock input EXTAL pin oscillation stabilization times For details of external clock input EXTAL pin and EXCL pin timing see table 31 5 and 31...

Page 1176: ...low level pulse width tCL 0 4 0 6 tcyc Clock high level pulse width tCH 0 4 0 6 tcyc Figure 31 4 External clock output stabilization delay time tDEXT 500 s Figure 31 8 Note tDEXT includes a RES pulse...

Page 1177: ...Page 1129 of 1178 REJ09B0403 0100 tCr tCL tCf tcyc tCH Figure 31 4 System Clock Timing tOSC1 tOSC1 VCC STBY RES Figure 31 5 Oscillation Stabilization Timing tOSC2 NMI IRQi i 0 to 15 Figure 31 6 Oscil...

Page 1178: ...EXH tEXL tEXr tEXf VCC 0 5 EXTAL Figure 31 7 External Clock Input Timing tDEXT RES Internal and external EXTAL STBY VCC 2 7 V VIH Note The external clock output stabilization delay time tDEXT includes...

Page 1179: ...Section 31 Electrical Characteristics Rev 1 00 Mar 12 2008 Page 1131 of 1178 REJ09B0403 0100 tEXCLH tEXCLL tEXCLr tEXCLf VCC 0 5 EXCL Figure 31 9 Subclock Input Timing...

Page 1180: ...ming Conditions VCC 3 0 V to 3 6 V VSS 0 V 20 MHz to 34 MHz Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns RES pulse width tRESW 20 tcyc Figure 31 10 NMI setup time tNMIS 150 ns...

Page 1181: ...Electrical Characteristics Rev 1 00 Mar 12 2008 Page 1133 of 1178 REJ09B0403 0100 tIRQS IRQ Edge input tIRQH tNMIS tNMIH tIRQS IRQ Level input NMI IRQi i 0 to 15 tNMIW tIRQW Figure 31 11 Interrupt In...

Page 1182: ...256 tCSD 14 7 AS delay time tASD 14 7 HBE delay time tHBD tAD 5 0 LBE delay time tLBD tAD 5 0 RD delay time 1 tRSD1 14 7 RD delay time 2 tRSD2 14 7 Read data setup time tRDS 14 7 Read data hold time t...

Page 1183: ...AS tRSD2 tAS tAH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD2 tWSW1 tWDD tWDH tAH T1 T2 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write tRDS tAS tAS tCSD Note AS is multiplexed with IOS Eith...

Page 1184: ...SD1 tASD tASD tAD tACC5 tRDH tWRD2 tWRD1 tWSW2 tWDD tWDH T1 T3 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write tWDS T2 tRDS tAH tAS Note AS is multiplexed with IOS Either the AS or IOS function c...

Page 1185: ...0100 AS tWTH T1 T2 RD Read D15 to D0 Read HWR LWR Write D15 to D0 Write WAIT Tw T3 tWTS tWTH tWTS Note AS is multiplexed with IOS Either the AS or IOS function can be selected by the IOSE bit of SYSC...

Page 1186: ...AH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD1 tWSW1 tWDD tWDH tAH T1 T2 RD Read Bus Cycle D15 to D8 D7 to D0 D7 to D0 WR Write Bus Cycle D15 to D8 tRDS tAS tAS tHBD tCSD IOS IOSE 1 CS256 CS256E...

Page 1187: ...tAH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD1 tWSW1 tWDD tWDH tAH T1 T2 RD Read Bus Cycle D15 to D8 D7 to D0 D7 to D0 WR Write Bus Cycle D15 to D8 tRDS tAS tAS tLBD tCSD IOS IOSE 1 CS256 CS256E...

Page 1188: ...tAS tAH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD1 tWSW1 tWDD tWDH tAH T1 T2 RD Read Bus Cycle D15 to D8 D7 to D0 D7 to D0 WR Write Bus Cycle D15 to D8 tRDS tAS tAS tLBD tHBD tCSD IOS IOSE 1 CS...

Page 1189: ...EJ09B0403 0100 AS tRSD2 tAS tAH tASD tASD tAD tACC3 tRDS tRDH T1 T2 RD Read D15 to D0 Read T2 or T3 T1 Note AS is multiplexed with IOS Either the AS or IOS function can be selected by the IOSE bit of...

Page 1190: ...2 of 1178 REJ09B0403 0100 tRSD2 tAD tACC1 tRDS tRDH T1 T2 or T3 T1 AS RD Read D15 to D0 Read Note AS is multiplexed with IOS Either the AS or IOS function can be selected by the IOSE bit of SYSCR A23...

Page 1191: ...time 2 tAS2 0 5 tcyc 14 7 31 21 Address hold time 2 tAH2 0 5 tcyc 9 7 CS delay time IOS CS256 tCSD 14 7 AH delay time tAHD 14 7 RD delay time 1 tRSD1 14 7 RD delay time 2 tRSD2 14 7 Read data setup ti...

Page 1192: ...J09B0403 0100 AH RD Read T1 T2 AD15 to AD0 Read D15 to D0 D15 to D0 A15 to A0 A15 to A0 HWR LWR Write AD15 to AD0 Write T3 T4 tCSD tAHD tRSD1 tACC2 tACC6 tAS2 tAD tAD tAH2 tWRD2 tWDD tWDH tRSD2 tWRD2...

Page 1193: ...0403 0100 T1 T2 T3 T4 T5 tCSD tAHD tRSD1 tACC4 tACC7 tAS2 tAD tAD tAH2 tWRD1 tWDD tWDH tWDS tRSD2 tWRD2 tWSW2 tRDS tRDH AH RD Read AD15 to AD0 Read D15 to D0 D15 to D0 A15 to A0 A15 to A0 HWR LWR Writ...

Page 1194: ...I O ports Output data delay time tPWD 29 4 ns Input data setup time tPRS 19 6 Input data hold time tPRH 19 6 Figure 31 22 PWMX Timer output delay time tPWOD 29 4 ns Figure 31 23 SCI Input clock cycle...

Page 1195: ...31 30 Slave 80 Figure 31 31 Clock low pulse width Master tLO 80 ns Slave 80 Clock rising time tRISE 20 ns Clock falling time tFALL 20 ns Data input setup time Master tSU 25 ns Slave 30 Data input hold...

Page 1196: ...D tPRH Ports 1 to 6 8 9 and A to F write Figure 31 22 I O Port Input Output Timing PWX3 to PWX0 tPWOD Figure 31 23 PWMX Output Timing tScyc tSCKr tSCKW SCK1 SCK3 tSCKf Figure 31 24 SCK Clock Input Tim...

Page 1197: ...S ADTRG Figure 31 26 A D Converter External Trigger Input Timing RESO tRESD tRESD tRESOW Figure 31 27 WDT Output Timing RESO SSCK output CPOS 0 SCS output SSCK output CPOS 1 SSO output SSI input tLEAD...

Page 1198: ...tSUcyc tLAG tOH tLO tHI tHI tLO tTD SSCK output CPOS 0 SCS output SSCK output CPOS 1 SSO output SSI input Figure 31 29 SSU Timing Master CPHS 0 tLEAD tFALL tRISE tSUcyc tLAG tTD tREL tOH tOD tSU tSA t...

Page 1199: ...cs Rev 1 00 Mar 12 2008 Page 1151 of 1178 REJ09B0403 0100 tLEAD tFALL tRISE tSUcyc tLAG tTD tREL tOH tOD tSU tSA tLO tHI tHI tLO tH SSCK input CPOS 0 SCS input SSCK input CPOS 1 SSO input SSI output F...

Page 1200: ...SDA input rise time tSr 7 5 SCL SDA input fall time tSf 300 ns SCL SDA output fall time tOf 20 0 1 Cb 250 SCL SDA input spike pulse elimination time tSP 1 tcyc SDA input bus free time tBUF 5 Start con...

Page 1201: ...ondition Sr Repeated start condition Figure 31 32 I2 C Bus Interface Input Output Timing Table 31 13 LPC Module Timing Conditions VCC 3 0 V to 3 6V VSS 0 V 20 MHz to 34 MHz Item Symbol Min Typ Max Uni...

Page 1202: ...8 Page 1154 of 1178 REJ09B0403 0100 LCLK LAD3 to LAD0 SERIRQ CLKRUN Transmit signal LAD3 to LAD0 SERIRQ CLKRUN LFRAME Receive signal tTXD tRXH tRXS tOFF LAD3 to LAD0 SERIRQ CLKRUN Transmit signal tLcy...

Page 1203: ...utput delay time Tco 2 5 12 5 RM_xxxx 1 setup time Tsu 3 RM_xxxx 1 hold time Thd 1 RM_xxxx 1 rise fall time Tr Tf 0 5 6 MDIO setup time tMDIOS 10 Figure 31 38 MDIO hold time tMDIOH 10 MDIO output data...

Page 1204: ...RM_TXD1 RM_TXD0 Tco Preamble Figure 31 35 RMII Transmit Timing SFD DATA CRC Tsu Thd Thd Tsu Preamble RM_REF CLK RM_CRS DV RM_RXD1 RM_RXD0 RM_RX ER L Figure 31 36 RMII Receive Timing Normal Operation S...

Page 1205: ...aracteristics Rev 1 00 Mar 12 2008 Page 1157 of 1178 REJ09B0403 0100 tMDIOh tMDIOs MDC MDIO Figure 31 38 MDIO Input Timing tMDIOdh MDC MDIO Figure 31 39 MDIO Output Timing tWOLd RM_REF CLK WOL Figure...

Page 1206: ...l Min Max Unit Test Conditions Input Input high voltage VIH 2 0 V Input low voltage VIL 0 8 V Figures 31 40 31 41 Differential input sensitivity VDI 0 2 V D D Differential common mode range VCM 0 8 2...

Page 1207: ...00 Mar 12 2008 Page 1159 of 1178 REJ09B0403 0100 USD USD Differential data lines Rise time Fall time 10 10 90 90 tR VCRS tF Figure 31 41 Data Signal Timing USD RS 22 USD Test point Test point RS 22 CL...

Page 1208: ...31 42 ETCK clock high pulse width tTCKH 15 ETCK clock low pulse width tTCKL 15 ETCK clock rise time tTCKr 5 ETCK clock fall time tTCKf 5 ETRST pulse width tTRSTW 20 tcyc Figure 31 43 Reset hold transi...

Page 1209: ...l Characteristics Rev 1 00 Mar 12 2008 Page 1161 of 1178 REJ09B0403 0100 ETRST ETCK RES tRSTHW tTRSTW Figure 31 44 Reset Hold Timing ETDO ETDI ETMS ETCK tTMSH tTMSS tTDIH tTDIS tTDOD Figure 31 45 JTAG...

Page 1210: ...0 V to 3 6 V AVCC 3 0 V to 3 6 V AVref 3 0 V to AVCC VSS AVSS 0 V 20 MHz to 34 MHz Condition A Condition B Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 Bits Conversion time 4 0 1 4 7...

Page 1211: ...2 kbyte block 600 1500 ms 64 kbyte block Programming time total 1 2 4 tP 9 2 24 s 512 kbytes Ta 25 C Erase time total 1 2 4 tE 9 2 24 Programming and Erase time total 1 2 4 tPE 18 4 48 Reprogramming c...

Page 1212: ...er stabilization One 0 1 F 0 47 F or two in parallel It is recommended that a bypass capacitor be connected to the VCC pin The values are reference values When connecting place a bypass capacitor near...

Page 1213: ...3 to 20 0 1 DDR 0 kept kept I O port A11 to A8 1 DDR 1 T T kept kept Address output Port 3 0 kept kept I O port D15 to D8 1 T T T T D15 to D8 Port 47 to 44 0 kept kept I O port A15 to A12 1 T T kept k...

Page 1214: ...OS Port 94 93 X T T kept kept I O port Port 92 0 kept kept I O port HBE 1 T T H H HBE Port 91 0 1 ADMXE 0 kept kept I O port AH 1 ADMXE 1 T T H H AH Port 90 0 kept kept I O port LBE 1 T T H H LBE Port...

Page 1215: ...t Legend H High level L Low level T High impedance kept Input port pins are in the high impedance state when DDR 0 and PCR 1 the input pull up MOS remains on Output port pins retain their states Funct...

Page 1216: ...ecifications R4F2472 F2472VBR34V 176 pin LFBGA PLBGA0176GA A H8S 2472 F ZTAT version wide temperature specifications R4F2472 F2472VBR34WV 176 pin LFBGA PLBGA0176GA A H8S 2462 F ZTAT version regular sp...

Page 1217: ...A BP 176 BP 176V 0 45g D E w S A w S B x4 v y1 S y S S A 1 A A B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e e Z E ZD A b B C D E F G H J K L M N P R x M S A B Dimension in Millimeters Min Nom Max Referenc...

Page 1218: ...0 21 8 22 2 22 0 21 8 1 7 A 0 15 0 1 0 05 0 65 0 5 0 35 L x 8 0 c 0 5 e 0 10 y HD HE A1 bp b1 c1 ZD ZE L1 P LQFP144 20x20 0 50 1 2g MASS Typ 144P6Q A FP 144L FP 144LV PLQP0144KA A RENESAS Code JEITA...

Page 1219: ...relative 53 Register direct 51 Register indirect 51 Register indirect with displacement 52 Register indirect with post Increment 52 Register indirect with pre decrement 52 ADI 909 Advanced mode 123 As...

Page 1220: ...ol register EXR 33 External clock 1053 F Flash erase block select parameter 945 Flash MAT configuration 921 Flash multipurpose address area parameter 942 Flash multipurpose data destination parameter...

Page 1221: ...65 Module stop mode 1072 Multi buffer frame transmit receive processing 830 Multiply accumulate register MAC 35 Multiprocessor communication function 460 N NMI interrupt 86 Normal mode 176 184 Number...

Page 1222: ...STS 848 DMA 850 DTCER 164 DTCERA 165 DTCERB 165 DTCERC 165 DTCERD 165 DTCERE 165 DTVECR 165 ECMR 761 ECSIPR 766 ECSR 764 EDMR 794 EDRRR 796 EDTRR 795 EESIPR 803 EESR 798 EPDR 845 EPDR0i 843 EPDR0o 844...

Page 1223: ...PR 775 MRA 162 MRB 163 MSTPCRA 1063 MSTPCRH 1062 MSTPCRL 1062 NCCS 203 209 249 286 292 333 OCRA 375 OCRAF 376 OCRAR 376 OCRB 375 ODR 689 P1DDR 192 275 P1DR 193 276 P1PCR 193 276 P2DDR 195 278 P2DR 196...

Page 1224: ...DR 712 SCIFCR 524 SCMR 444 SCR 437 SDBPR 1024 SDBSR 1024 SDIDR 1042 SDIR 1023 SERIRQ 747 SIRQCR 699 SMICCSR 714 SMICDTR 714 SMICFLG 713 SMICIR 715 SMR 434 SSCR2 561 SSCRH 554 SSCRL 556 SSER 558 SSMR 5...

Page 1225: ...429 Software protection 984 Software standby mode 1069 SSU mode 568 Stack pointer SP 32 Stack status 75 Stall operations 883 Start condition 618 Status stage 876 Stop condition 618 Synchronous serial...

Page 1226: ...Rev 1 00 Mar 12 2008 Page 1178 of 1178 REJ09B0403 0100...

Page 1227: ...2462 Group Publication Date Rev 1 00 Mar 12 2008 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solu...

Page 1228: ...7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2377 3473 Renesas Technology Taiwan Co...

Page 1229: ......

Page 1230: ...H8S 2472 Group H8S 2462 Group Hardware Manual...

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