Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 858 of 1178
REJ09B0403-0100
•
EPIR04
Bit Bit
Name
Initial
Value
R/W Description
7 to 0
D7 to D0
Undefined W
Endpoint FIFO Number
[Possible setting range]
0 to 3
The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number
corresponds to the endpoint number described in this manual. Thus data transfer between the USB
host and the endpoint FIFO can be enabled by putting the endpoint number and the endpoint FIFO
number in one-to-one correspondence. Note that the setting value is subject to a limitation
described below.
Since each endpoint FIFO number is optimized by the exclusive software that corresponds to the
transfer system, direction, and the maximum packet size, make sure to set the endpoint FIFO
number to the data described in table 22.2.
1. The endpoint FIFO number 1 cannot designate other than the maximum packed size of 8 bytes,
control transfer method, and out transfer direction.
2. The endpoint number 0 and the endpoint FIFO number must have one-on one relationship.
3. The maximum packet size for the endpoint FIFO number 0 is 8 bytes only.
4. The endpoint FIFO number 0 can specify only the maximum packet size and the data for the
rest should be all 0.
5. The maximum packet size for the endpoint FIFO numbers 1 and 2 is limited to 64 bytes.
6. The maximum packet size for the endpoint FIFO numbers 3 is limited to 8 bytes.
7. The maximum number of endpoint information setting is ten.
8. Up to ten endpoint information setting should be made.
9. Write 0 to the endpoints not in use.
Table 22.2 shows the example of limitations for the maximum packet size, the transfer method,
and the transfer direction.
Table 22.2 Example of Limitations for Setting Values
Endpoint FIFO Number
Maximum Packet Size
Transfer Method
Transfer Direction
0 8
bytes
Control
1 64
bytes
Bulk
Out
2 64
bytes
Bulk
In
3 8
bytes
Interrupt
In
Summary of Contents for H8S Family
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Page 70: ...Section 1 Overview Rev 1 00 Mar 12 2008 Page 22 of 1178 REJ09B0403 0100...
Page 108: ...Section 2 CPU Rev 1 00 Mar 12 2008 Page 60 of 1178 REJ09B0403 0100...
Page 116: ...Section 3 MCU Operating Modes Rev 1 00 Mar 12 2008 Page 68 of 1178 REJ09B0403 0100...
Page 152: ...Section 5 Interrupt Controller Rev 1 00 Mar 12 2008 Page 104 of 1178 REJ09B0403 0100...
Page 206: ...Section 6 Bus Controller BSC Rev 1 00 Mar 12 2008 Page 158 of 1178 REJ09B0403 0100...
Page 420: ...Section 9 14 Bit PWM Timer PWMX Rev 1 00 Mar 12 2008 Page 372 of 1178 REJ09B0403 0100...
Page 476: ...Section 12 Watchdog Timer WDT Rev 1 00 Mar 12 2008 Page 428 of 1178 REJ09B0403 0100...
Page 552: ...Section 14 CRC Operation Circuit CRC Rev 1 00 Mar 12 2008 Page 504 of 1178 REJ09B0403 0100...
Page 712: ...Section 18 I2 C Bus Interface IIC Rev 1 00 Mar 12 2008 Page 664 of 1178 REJ09B0403 0100...
Page 804: ...Section 19 LPC Interface LPC Rev 1 00 Mar 12 2008 Page 756 of 1178 REJ09B0403 0100...
Page 838: ...Section 20 Ethernet Controller EtherC Rev 1 00 Mar 12 2008 Page 790 of 1178 REJ09B0403 0100...
Page 964: ...Section 24 RAM Rev 1 00 Mar 12 2008 Page 916 of 1178 REJ09B0403 0100...
Page 1066: ...Section 25 Flash Memory Rev 1 00 Mar 12 2008 Page 1018 of 1178 REJ09B0403 0100...
Page 1098: ...Section 26 Boundary Scan JTAG Rev 1 00 Mar 12 2008 Page 1050 of 1178 REJ09B0403 0100...
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Page 1230: ...H8S 2472 Group H8S 2462 Group Hardware Manual...