Renesas H8S Family, Hardware Manual

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Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Mar. 12, 2008 Page 528 of 1178
REJ09B0403-0100
15.4.3 Initialization of the SCIF
(1) Initialization of the SCIF
Use an example of the flowchart in figure 15.3 to initialize the SCIF before transmitting or
receiving data.
End of Initialization
Start initialization
Clear module stop
Set SCIFCR
Set DLAB bit in FLCR to 1
Set FDLH and FDLL
Clear DLAB bit in FLCR to 0
Set data transfer format in FLCR
Set interrupt enable bits in FIER
Set FIFOE bit in FFCR to 1
Set receive FIFO trigger level in FFCR
Set XMITFRST and RCVRFRST bits
in FFCR to 1 to reset FIFOs
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
[9]
[9]
[6]
[7]
[8]
[6]
[7]
[8]
FIFOs used?
Yes
No
Select an input clock with the CKSEL1 and
CKSEL0 bits in SCIFCR. Set the SCIF input/
output pins with the SCIFOE1 and SCIFOE0
bits in SCIFCR.
Set the DLAB bit in FLCR to 1 to enable
access to FDLL and FDLH.
The initial value of FDLL and FDLH is 0.
Set a value within the range from 1 to 65535.
Clear the DLAB bit in FLCR to 0 to disable
access to FDLL and FDLH.
Select parity with the EPS and PEN bits in
FLCR, and set the stop bit with the STOP bit
in FLCR. Then, set the data length with the
CLS1 and CLS0 bits in FLCR.
When FIFOs are used, set the FIFOE bit in
FFCR to 1.
Set the receive FIFO trigger level with the
RCVRTRIG1 and RCVRTRIG0 bits in FFCR.
Set the XMITFRST and RCVRFRST bits in
FFCR to 1 to reset the FIFOs.
Enable or disable an interrupt with the
EDSSI, ELSI, ETBEI, and ERBFI bits in
FIER and the OUT2 bit in FMCR.
Figure 15.3 Example of Initialization Flowchart