Renesas H8S Family, Hardware Manual

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Section 27 Clock Pulse Generator
Rev. 1.00 Mar. 12, 2008 Page 1051 of 1178
REJ09B0403-0100
Section 27 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (
φ
), internal clock,
bus master clock, and subclock (
φ
SUB). The clock pulse generator consists of an oscillator, PLL
multiplier circuit, system clock select circuit, medium-speed clock divider, bus master clock select
circuit, subclock input circuit, and subclock waveform shaping circuit. Figure 27.1 shows a block
diagram of the clock pulse generator.
WDT_1
count clock
φ
φ
/2
to
φ
/32
φ
SUB
EXTAL
XTAL
EXCL
Subclock
input circuit
Subclock
waveform
shaping
circuit
PLL
multiplier
circuit
Oscillator
System clock
to
φ
pin
Internal clock
to peripheral
modules
Bus master clock
to CPU and DTC
System clock
select circuit
Medium-
speed clock
divider
Bus master
clock select
circuit
φ
Figure 27.1 Block Diagram of Clock Pulse Generator
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. Use of the
medium-speed clock (
φ
/2 to
φ
/32) may be limited during CPU operation and when accessing the
internal memory of the CPU. The operation speed of the DTC and the external space access cycle
are thus stabilized regardless of the setting of medium-speed mode. For details on the standby
control register, see section 28.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, see section 28.1.2, Low-Power
Control Register (LPWRCR).