CAN Control Registers
1584
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Controller Area Network (CAN)
Table 23-6. Error and Status Register Field Descriptions (continued)
Bit
Field
Value
Description
8
PER
Parity Error Detected
0
No parity error has been detected since last read access.
1
The parity check mechanism has detected a parity error in the Message RAM. This bit will be reset
if Error and Status Register is read.
7
BOff
Bus-Off State
0
The CAN module is not in Bus-Off state.
1
The CAN module is in Bus-Off state.
6
EWarn
Warning State
0
Both error counters are below the error warning limit of 96.
1
At least one of the error counters has reached the error warning limit of 96.
5
EPass
Error Passive State
0
On CAN Bus error, the CAN could send active error frames.
1
The CAN Core is in the error passive state as defined in the CAN Specification.
4
RxOk
Received a message successfully
0
No message has been successfully received since the last time when this bit was read by the CPU.
This bit is never reset by CAN internal events.
1
A message has been successfully received since the last time when this bit was reset by a read
access of the CPU (independent of the result of acceptance filtering). This bit will be reset if Error
and Status Register is read.
3
TxOk
Transmitted a message successfully
0
No message has been successfully transmitted since the last time when this bit was read by the
CPU. This bit is never reset by CAN internal events.
1
A message has been successfully transmitted (error free and acknowledged by at least one other
node) since the last time when this bit was reset by a read access of the CPU. This bit will be reset
if Error and Status Register is read.
2-0
LEC
Last Error Code The LEC field indicates the type of the last error on the CAN bus. This field will be
cleared to '0' when a message has been transferred (reception or transmission) without error.
0
No Error
1
Stuff Error: More than five equal bits in a row have been detected in a part of a received message
where this is not allowed.
2
Form Error: A fixed format part of a received frame has the wrong format.
3
Ack Error: The message this CAN Core transmitted was not acknowledged by another node.
4
Bit1 Error: During the transmission of a message (with the excep-tion of the arbitration field), the
device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was
dominant.
5
Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, or
overload flag), the device wanted to send a dominant level (logical value '0'), but the monitored bus
level was recessive. During Bus-Off recovery, this status is set each time a sequence of 11
recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus-Off
recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6
CRC Error: In a received message, the CRC check sum was incorrect. (CRC received for an
incoming message does not match the calculated CRC for the received data).
7
No CAN bus event was detected since the last time when CPU has read the Error and Status
Register. Any read access to the Error and Status Register re-initializes the LEC to value '7'.
Interrupts are generated by bits PER, BOff and EWarn (if EIE bit in CAN Control Register is set) and by
bits WakeUpPnd, RxOk, TxOk, and LEC (if SIE bit in CAN Control Register is set).
A change of bit EPass will not generate an Interrupt.
NOTE:
Reading the Error and Status Register clears the WakeUpPnd, PER, RxOk and TxOk bits
and sets the LEC to value '7'. Additionally, the Status Interrupt value (0x8000) in the Interrupt
Register will be replaced by the next lower priority interrupt value.
