SCI Registers
1042
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Serial Communications Interface (SCI)
Table 13-17. SCI FIFO Control (SCIFFCT) Register Field Descriptions (continued)
Bit
Field
Value
Description
7
−
0
FFTXDLY7
−
0
FIFO transfer delay. These bits define the delay between every transfer from FIFO transmit buffer
to transmit shift register. The delay is defined in the number of SCI serial baud clock cycles. The 8
bit register could define a minimum delay of 0 baud clock cycles and a maximum of 256 baud clock
cycles
In FIFO mode, the buffer (TXBUF) between the shift register and the FIFO should be filled only
after the shift register has completed shifting of the last bit. This is required to pass on the delay
between transfers to the data stream. In FIFO mode, TXBUF should not be treated as one
additional level of buffer. The delayed transmit feature will help to create an auto-flow scheme
without RTS/CTS controls as in standard UARTS.
When SCI is configured for one stop-bit, delay introduced by FFTXDLY between one frame and the
next frame is equal to number of baud clock cycles that FFTXDLY is set to.
When SCI is configured for two stop-bits, delay introduced by FFTXDLY between one frame and
the next frame is equal to number of baud clock cycles that FFTXDLY is set to minus 1.
