Low Power Modes
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SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
System Control and Interrupts
1.9.1.1.1.2 WAIT For EVENT
The wait for event instruction, WFE, causes entry to sleep mode depending on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the register
is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor
clears the register and continues executing instructions without entering sleep mode. If the event register
is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation
occurs if an SEV instruction has been executed. Software cannot access this register directly. See the
Cortex™-M3 Instruction Set Technical User's Manual for more information.
1.9.1.1.1.3 SLEEP-ON-EXIT
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of an
exception handler, it returns to thread mode and immediately enters sleep mode. This mechanism can be
used in applications that only require the processor to run when an exception occurs.
1.9.1.1.1.4 WAKE UP From Low-Power Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter low-power
mode.
1.9.1.1.1.5 WAKE UP From WFI or SLEEP-ON-EXIT
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause
exception entry. Some embedded systems might have to execute system restore tasks after the processor
wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by
setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a
higher priority than a current exception priority, the processor wakes up but does not execute the interrupt
handler until the processor clears the PRIMASK bit. For more information about the PRIMASK and
FAULTMASK registers, refer to the register descriptions section under the
Cortex-M3 Processor
,
Programming Model section.
1.9.1.1.1.6 WAKE UP FROM WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In
addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an
event and wakes up the processor even if the interrupt is disabled or has insufficient priority to cause
exception entry. For more information about SYSCTRL, Please refer to the register description under the
System Control Block section of the Cortex-M3 Peripherals chapter.
NOTE:
When the M3 subsystem and the device are in deep-sleep mode, wake-up should only
happen from the M3 subsystem since it is the master. Wake-up should not happen from the
C28 subsystem. This needs to be taken care of by the application.
The clocking is explained in detail in the Clock Control section. For more information about the clocking of
the sleep modes, see the Master Subsystem Clocking and Control Subsystem Clocking sections. For
more details on M3 power modes, please refer to the
Power Management Chapter of the Cortex™-M3
Technical Reference Manual
.
1.9.1.2
Control Subsystem Low-Power Modes Configuration
summarizes the various low-power modes.
