µDMA Channel Control Structure
1211
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Micro Direct Memory Access ( µDMA)
Table 16-16. DMA Channel Control Word (DMACHCTL) Register Field Descriptions (continued)
Bit
Field
Value
Description
13-4
XFERSIZE
Transfer Size (minus 1)
This field configures the total number of items to transfer. The value of this field is 1 less than the
number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023
which represents a transfer size of 1024 items.
The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then
this value is the number of 32-bit words to transfer.
The µDMA controller updates this field immediately prior to entering the arbitration process, so it
contains the number of outstanding items that is necessary to complete the µDMA cycle.
3
NXTUSEBURST
Next Useburst
This field controls whether the Useburst SET[n] bit is automatically set for the last transfer of a
peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items
to transfer is less than the arbitration size, the µDMA controller uses single transfers to complete
the transaction. If this bit is set, then the controller uses a burst transfer to complete the last
transfer.
2-0
XFERMODE
µDMA Transfer Mode
This field configures the operating mode of the µDMA cycle. Refer to
for a detailed
explanation of transfer modes.
Because this register is in system RAM, it has no reset value. Therefore, this field should be
initialized to 0 before the channel is enabled.
0x0
Stop
0x1
Basic
0x2
Auto-Request
0x3
Ping-Pong
0x4
Memory Scatter-Gather
0x5
Alternate Memory Scatter-Gather
0x6
Peripheral Scatter-Gather
0x7
Alternate Peripheral Scatter-Gather
XFERMODE Bit Field Values
Stop
Channel is stopped or configuration data is invalid. No more transfers can occur.
Basic
For each trigger (whether from a peripheral or a software request), the µDMA controller performs the
number of transfers specified by the ARBSIZE field.
Auto-Request
The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of
XFERSIZE items without any further requests.
Ping-Pong
This mode uses both the primary and alternate control structures for this channel. When the number of
transfers specified by the XFERSIZE field have completed for the current control structure (primary or
alternate), the µDMA controller switches to the other one. These switches continue until one of the control
structures is not set to ping-pong mode. At that point, the µDMA controller stops. An interrupt is generated
on completion of the transfers configured by each control structure. See
Memory Scatter-Gather
When using this mode, the primary control structure for the channel is configured to allow a list of
operations (tasks) to be performed. The source address pointer specifies the start of a table of tasks to be
copied to the alternate control structure for this channel. The XFERMODE field for the alternate control
structure should be configured to 0x5 (Alternate memory scatter-gather) to perform the task. When the
task completes, the  µDMA switches back to the primary channel control structure, which then copies the
next task to the alternate control structure. This process continues until the table of tasks is empty. The
last task must have an XFERMODE value other than 0x5. Note that for continuous operation, the last task
can update the primary channel control structure back to the start of the list or to another list. See
