Programming Model
1612
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Cortex-M3 Processor
Table 24-8. Program Status Register (PSR) Field Descriptions (continued)
Bit
Field
Value
Description
27
Q
APSR DSP Overflow and Saturation Flag
0
DSP overflow or saturation has not occurred since reset or since the bit was last cleared.
1
DSP Overflow or saturation has occurred. DSP overflow or saturation has not occurred since
The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by
software using an MRS instruction.
26-25
ICI / IT
EPSR ICI / IT status
Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution
state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The
If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the
block is conditional.
The conditions for the instructions are either all the same, or some can be the inverse of others.
See the Cortex-M3 Instruction Set Technical User's Manual for more information. The value of this
field is only meaningful when accessing PSR or EPSR.
24
THUMB
1
EPSR Thumb State. This bit indicates the Thumb state and should always be set. The following can
clear the THUMB bit:
• The BLX, BX and POP{PC} instructions
• Restoration from the stacked xPSR value on an exception return
• Bit 0 of the vector value on an exception entry
Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on
page 116 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23-16
Reserved
Reserved
15-10
ICI / IT
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an
interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the
processor stops the load multiple or store multiple instruction operation temporarily and stores the
next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load
or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction
in the block is conditional. The conditions for the instructions are either all the same, or some can
be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more
information.
The value of this field is only meaningful when accessing PSR or EPSR.
9-7
Reserved
Reserved
