Emulation and Reset Considerations
1152
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Multichannel Buffered Serial Port (McBSP)
15.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
When the McBSP is reset in either of the above two ways, the machine is reset to its initial state, including
reset of all counters and status bits. The receive status bits include RFULL, RRDY, and RSYNCERR. The
transmit status bits include XEMPTY, XRDY, and XSYNCERR.
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Device reset. When the whole DSP is reset (XRS signal is driven low), all McBSP pins are in GPIO
mode. When the device is pulled out of reset, the clock to the McBSP modules remains disabled.
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McBSP reset. When the receiver and transmitter reset bits, RRST and XRST, are loaded with 0s, the
respective portions of the McBSP are reset and activity in the corresponding section of the serial port
stops. Input-only pins such as MDRx, and all other pins that are configured as inputs are in a known
state. The MFSRx and MFSXx pins are driven to their inactive state if they are not outputs. If the
MCLKR and MCLKX pins are programmed as outputs, they are driven by CLKG, provided that GRST
= 1. Lastly, the MDXx pin is in the high-impedance state when the transmitter and/or the device is
reset.
During normal operation, the sample rate generator is reset if the GRST bit is cleared. GRST must be
0 only when neither the transmitter nor the receiver is using the sample rate generator. In this case,
the internal sample rate generator clock (CLKG) and its frame-synchronization signal (FSG) are driven
inactive low.
When the sample rate generator is not in the reset state (GRST = 1), pins MFSRx and MFSXx are in
an inactive state when RRST = 0 and XRST = 0, respectively, even if they are outputs driven by FSG.
This ensures that when only one portion of the McBSP is in reset, the other portion can continue
operation when GRST = 1 and its frame synchronization is driven by FSG.
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Sample rate generator reset. The sample rate generator is reset when GRST is loaded with 0.
When neither the transmitter nor the receiver is fed by CLKG and FSG, you can reset the sample rate
generator by clearing GRST. In this case, CLKG and FSG are driven inactive low. If you then set
GRST, CLKG starts and runs as programmed. Later, if GRST = 1, FSG pulses active high after the
programmed number of CLKG cycles has elapsed.
15.10.2.3 McBSP Initialization Procedure
The serial port initialization procedure is as follows:
1. Make XRST = RRST = GRST = 0 in SPCR[1,2]. If coming out of a device reset, this step is not
required.
2. While the serial port is in the reset state, program only the McBSP configuration registers (not the data
registers) as required.
3. Wait for two clock cycles. This ensures proper internal synchronization.
4. Set up data acquisition as required (such as writing to DXR[1,2]).
5. Make XRST = RRST = 1 to enable the serial port. Make sure that as you set these reset bits, you do
not modify any of the other bits in SPCR1 and SPCR2. Otherwise, you change the configuration you
selected in step 2.
6. Set FRST = 1, if internally generated frame synchronization is required.
7. Wait two clock cycles for the receiver and transmitter to become active.
Alternatively, on either write (step 1 or 5), the transmitter and receiver can be placed in or taken out of
reset individually by modifying the desired bit.
The above procedure for reset/initialization can be applied in general when the receiver or transmitter
must be reset during its normal operation and when the sample rate generator is not used for either
operation.
