Functional Description
1200
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Micro Direct Memory Access ( µDMA)
16.3.7 Transfer Size and Increment
The µDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination data size
must be the same for any given transfer. The source and destination address can be auto-incremented by
bytes, half-words, or words, or can be set to no increment. The source and destination address increment
values can be set independently, and it is not necessary for the address increment to match the data size
as long as the increment is the same or larger than the data size. For example, it is possible to perform a
transfer using 8-bit data size, but using an address increment of full words (4 bytes). The data to be
transferred must be aligned in memory according to the data size (8, 16, or 32 bits).
shows the configuration to read from a peripheral that supplies 8-bit data.
Table 16-5. µDMA Read Example: 8-Bit Peripheral
Field
Configuration
Source data size
8 bits
Destination data size
8 bits
Source address increment
No increment
Destination address increment
Byte
Source end pointer
Peripheral read FIFO register
Destination end pointer
End of the data buffer in memory
16.3.8 Peripheral Interface
Each peripheral that supports µDMA has a single request and/or burst request signal that is asserted
when the peripheral is ready to transfer data (see
). The request signal can be disabled or
enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request
Mask Clear (DMAREQMASKCLR) registers. The µDMA request signal is disabled, or masked, when the
channel request mask bit is set. When the request is not masked, the µDMA channel is configured
correctly and enabled, and the peripheral asserts the request signal, the µDMA controller begins the
transfer.
NOTE:
When using
μ
DMA to transfer data to and from a peripheral, the peripheral must disable all
interrupts to the NVIC.
When a µDMA transfer is complete, the µDMA controller generates an interrupt. See
for
more information.
For more information on how a specific peripheral interacts with the µDMA controller, refer to the
DMA
Operation
section in the chapter that discusses that peripheral.
16.3.9 Software Request
One µDMA channel is dedicated to software-initiated transfers. A transfer is initiated by software by first
configuring and enabling the transfer, and then issuing a software request using the DMA Channel
Software Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should
be used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. Any channel may be
used for software requests as long as the corresponding peripheral is not using µDMA for data transfer.
Upon completion of a µDMA transfer initiated by SW on any channel, a completion interrupt occurs on the
software interrupt vector.
