System Control Registers
283
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
System Control and Interrupts
Table 1-178. M3 to C28 Core Flag (MTOCIPCFLG) Register Field Descriptions (continued)
Bit
Field
Value
Description
4
IPC5
0
MTOCIPCFLG Flag 5. M3 to C28 core IPC flag 5 status. The bit is ‘1’ if the corresponding
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a ‘1."
3
IPC4
0
MTOCIPCFLG Interrupt 4. M3 to C28 IPC interrupt 4 status flag. The bit is ‘1’ if the corresponding
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a ‘1."
2
IPC3
0
MTOCIPCFLG Interrupt 3. M3 to C28 IPC interrupt 3 status flag. The bit is ‘1’ if the corresponding
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a ‘1."
1
IPC2
0
MTOCIPCFLG Interrupt 2. M3 to C28 IPC interrupt 2 status flag. The bit is ‘1’ if the corresponding
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a ‘1."
0
IPC1
0
MTOCIPCFLG Interrupt 1. M3 to C28 IPC interrupt 1 status flag. The bit is ‘1’ if the corresponding
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a ‘1."
1.13.11.4 C28 to M3 Core IPC Acknowledge (CTOMIPCACK) Register
Figure 1-167. M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register
31
30
29
28
27
26
25
24
IPC32
IPC31
IPC30
IPC29
IPC28
IPC27
IPC26
IPC25
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
23
22
21
20
19
18
17
16
IPC24
IPC23
IPC22
IPC21
IPC20
IPC19
IPC18
IPC17
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
IPC16
IPC15
IPC14
IPC13
IPC12
IPC11
IPC10
IPC9
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
7
6
5
4
3
2
1
0
IPC8
IPC7
IPC6
IPC5
IPC4
IPC3
IPC2
IPC1
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-179. M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register Field Descriptions
Bit
Field
Value
Description
31
IPC32
0
CTOMIPCACK Flag 32. C28 to M3 core IPC flag 32 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
30
IPC31
0
CTOMIPCACK Flag 31. C28 to M3 core IPC flag 31 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
29
IPC30
0
CTOMIPCACK Flag 30. C28 to M3 core IPC flag 30 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
28
IPC29
0
CTOMIPCACK Flag 29. C28 to M3 core IPC flag 29 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers
27
IPC28
0
CTOMIPCACK Flag 28. C28 to M3 core IPC flag 28 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
26
IPC27
0
CTOMIPCACK Flag 27. C28 to M3 core IPC flag 27 acknowledge. Writing a ‘1’ to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
